Quality of service scheduling for simultaneous multi-threaded processors

• US 8,869,153 B2
• Filed: 05/30/2008
• Issued: 10/21/2014
• Est. Priority Date: 07/19/2006
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Krieger, Orran Y., Rosenburg, Bryan S., Tremaine, Robert B., Wisniewski, Robert W.
• Primary Examiner(s): ZHE, MENG YAO
• Application Number:
  US12/130,612
• Publication Number:
  US 20080229321A1
• Time in Patent Office: 2,335 Days
• US Class Current: 718/102
• CPC Class Codes: G06F 2209/5018 Thread allocation
• CPC Class Codes: G06F 2209/5019 Workload prediction
• CPC Class Codes: G06F 2209/508 Monitor
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/505 considering the load

Abstract

A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees.

Claims

1. A method of providing quality of service scheduling in multithreaded processing, comprising:

identifying a plurality of hardware resources utilized by a hardware thread and its corresponding software thread in simultaneous multithreaded processing, the plurality of hardware resources including at least a plurality of floating point units, a decoder, and an L1 cache wherein the hardware thread'"'"'s usage information is tracked individually for each of the plurality of floating point units, the decoder, and the L1 cache;

communicating by hardware to an operating system the identified one or more hardware resource utilization; and

allowing reservation by the operating system of the one or more hardware resources for a software thread in the simultaneous multithreaded processing based on individually tracked usage information of said each of the plurality of floating point units, the decoder, and the L1 cache,

wherein communication between the hardware and the operating system is achieved by using a mapping stored in a core that allows the operating system to log a software thread identifier, and the hardware to inserts a corresponding hardware thread identifier when the hardware executes the software thread.

2. The method of claim 1, wherein the step of identifying includes identifying one or more hardware resources utilized by a set of threads in simultaneous multithreaded processing.

3. The method of claim 1, wherein the step of identifying is performed by hardware.

4. The method of claim 1, wherein the step of communicating includes storing information pertaining to the identified one or more hardware resource utilization.

5. The method of claim 1, wherein the one or more hardware resources include one or more processing elements, functional units or cache memory or combination thereof.

6. The method of claim 1, wherein the one or more hardware resources further includes at least an integer unit, an arithmetic logic unit, a shifter, a register, a load-store unit, cache memory or combination thereof.

7. The method of claim 1, further including:

scheduling one or more threads based on information associated with the identified one or more hardware resource utilization.

8. The method of claim 7, wherein the step of scheduling is performed by an operating system.

9. The method of claim 1, further including:

reserving one or more hardware resources for a thread based on information associated with the identified one or more hardware resource utilization.

10. The method of claim 9, wherein the step of reserving is performed by an operating system.

11. The method of claim 9, wherein the step of reserving includes storing one or more data bits in a register accessible by hardware, the data bits identifying which one or more hardware resources to reserve for a thread.

12. The method of claim 1, wherein the step of communicating includes storing in a register accessible by an operating system, one or more data bits that identify one or more hardware resource utilization by a thread.

13. The method of claim 12, wherein the step of storing is performed by hardware.

14. The method of claim 1, further including:

analyzing information associated with the identified one or more hardware resource utilization by a thread.

15. The method of claim 1, further including:

restricting one or more hardware resources from a thread based on information associated with the identified one or more hardware resource utilization.

16. A method of providing quality of service scheduling in multithreaded processing, comprising:

accessing, by an operating system, information associated with hardware resource utilization per hardware thread and its corresponding software thread in simultaneous multithreaded processing, information tracked by hardware associated with hardware resource utilization including the hardware thread'"'"'s usage information tracked individually for each of a plurality of floating point units, a decoder, and an L1 cache, wherein a counter is kept for each of the floating point units to track usage of said each of the floating point units individually, the information indicating which hardware threads on a core have used which hardware resources on the core; and

scheduling by the operating system one or more software threads based on the information,

wherein the accessing by the operating system is achieved by using a mapping stored in the core that allows the operating system to log a software thread identifier, and the hardware to insert a corresponding hardware thread identifier responsive to the hardware executing the software thread.

17. The method of claim 16, further including:

analyzing the information to determine at least one of memory utilization pattern, thread affinity concern, thread interference issue, and other thread resource behavior affecting utilization, and the step of scheduling includes scheduling one or more threads based on at least one of memory utilization pattern, thread affinity concern, thread interference issue, and other thread resource utilization affection behavior.

18. A method of providing quality of service scheduling in multithreaded processing, comprising:

accessing, by an operating system, information tracked by hardware associated with a software thread'"'"'s and its corresponding hardware thread'"'"'s use of a plurality of hardware resources on a core in simultaneous multithreaded processing, the plurality of hardware resources including at least a plurality of floating point units, a decoder, and an L1 cache wherein the hardware thread'"'"'s usage information is tracked individually for each of the plurality of floating units, the decoder, and the L1 cache, wherein a counter is kept for each of the floating point units to track usage of said each of the floating point units individually, the information indicating which hardware threads on the core have used which hardware resources on the core; and

reserving by the operating system one or more hardware resources for a software thread based on the accessed information,

wherein the accessing by the operating system is achieved by using a mapping stored in the core that allows the operating system to log a software thread identifier, and the hardware to insert a corresponding hardware thread identifier responsive to the hardware executing the software thread.

19. A system for providing quality of service scheduling in multithreaded processing, comprising:

a hardware controller on a processor operable to track a hardware thread'"'"'s and its corresponding software thread'"'"'s use of a plurality of hardware resources in simultaneous multithreaded processing, the plurality of hardware resources including at least a plurality of floating point units, a decoder, and an L1 cache, wherein the hardware thread'"'"'s usage information is tracked individually for each of the plurality of floating point units, the decoder, and the L1 cache,

the hardware controller further operable to communicate information associated with the use of one or more hardware resources per hardware thread to an operating system;

the operating system operable to access the information and schedule one or more software threads based on individually tracked usage information of said each of the plurality of floating point units, the decoder, and the L1 cache,

wherein communication between the hardware controller and the operating system is achieved by using a mapping stored in a core that allows the operating system to log a software thread identifier, and the hardware controller to insert a corresponding hardware thread identifier responsive to the hardware controller executing the software thread.