Wafer encapsulated microelectromechanical structure and method of manufacturing same

• US 8,871,551 B2
• Filed: 11/06/2006
• Issued: 10/28/2014
• Est. Priority Date: 01/20/2006
• Status: Active Grant

• Current Assignee: SiTime Corporation (Megachips Corporation)
• Original Assignee: SiTime Corporation (Megachips Corporation)
• Inventors: Partridge, Aaron, Lutz, Markus, Gupta, Pavan
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US11/593,404
• Publication Number:
  US 20070172976A1
• Time in Patent Office: 2,913 Days
• Field of Search: 438/615, 438/616, 438/619, 438/621, 438/684, 438/698, 438/700, 438/777, 438/51, 438/52, 438/53, 438/456, 257/E23.128, 257/E23.067
• US Class Current: 438/51
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2203/04 Electrodes
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 7/0035 for maintaining a controlled atmosphere inside of the chamber containing the MEMS
• CPC Class Codes: B81B 7/0058 for protecting against damages due to external chemical or mechanical influences, e.g. shocks or vibrations
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 1/00277 for maintaining a controlled atmosphere inside of the cavity containing the MEMS
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2201/0171 Doping materials
• CPC Class Codes: B81C 2203/031 Anodic bondings
• CPC Class Codes: B81C 2203/036 Fusion bonding
• CPC Class Codes: B81C 2203/037 Thermal bonding techniques not provided for in B81C2203/035 - B81C2203/036
• CPC Class Codes: B81C 2203/038 Bonding techniques not provided for in B81C2203/031 - B81C2203/037
• CPC Class Codes: H01L 23/051 another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10N 30/306 Cantilevers

Abstract

There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or resonator. The fabricating or manufacturing microelectromechanical systems of the present invention, and the systems manufactured thereby, employ wafer bonding encapsulation techniques.

Claims

1. A method comprising:

forming a cavity in a first substrate;

depositing an intermediate layer on the first substrate after forming the cavity;

securing a second substrate to the intermediate layer;

forming a microelectromechanical structure in a portion of the second substrate;

encapsulating the microelectromechanical structure; and

wherein forming the microelectromechanical structure in the portion of the second substrate comprises forming the microelectromechanical structure in the portion of the second substrate before securing the second substrate to the intermediate layer.

2. The method of claim 1 wherein the first substrate comprises carbon, polycrystalline silicon, monocrystalline silicon, amorphous silicon, silicon carbide, silicon/germanium, germanium, and/or gallium arsenide.

3. The method of claim 1 wherein forming a cavity in a first substrate comprises forming a cavity in a first substrate using lithography and etching.

4. The method of claim 1 wherein forming a cavity in a first substrate comprises forming a cavity that includes a depth of about 1 μ

m in a first substrate.

5. The method of claim 1 wherein depositing or growing an intermediate layer on the first substrate comprises growing an intermediate layer on the first substrate.

7. The method of claim 1 wherein depositing or growing an intermediate layer on the first substrate comprises depositing or growing a native oxide on the first substrate.

8. The method of claim 1 wherein depositing or growing an intermediate layer on the first substrate comprises depositing or growing a thin insulating layer on the first substrate.

9. The method of claim 1 wherein the second substrate comprises carbon, polycrystalline silicon, monocrystalline silicon, amorphous silicon, silicon carbide, silicon/germanium, germanium, or gallium arsenide.

10. The method of claim 1 wherein securing a second substrate to the intermediate layer comprises bonding a second substrate to the intermediate layer.

11. The method of claim 10 wherein bonding a second substrate to the intermediate layer comprises fusion bonding and/or anodic-like bonding a second substrate to the intermediate layer.

12. The method of claim 1 further comprising forming a contact, wherein a first portion of the contact is formed from a portion of the second substrate.

13. The method of claim 1 wherein a surface of the intermediate layer forms a wall of the chamber.

14. The method of claim 1 further comprising forming a cavity in the second substrate, wherein the cavity in the second substrate forms a portion of the chamber.

6. A method comprising:

forming a cavity in a first substrate;

depositing an intermediate layer on the first substrate after forming the cavity;

securing a second substrate to the intermediate layer;

forming a microelectromechanical structure in a portion of the second substrate;

encapsulating the microelectromechanical structure; and

wherein depositing or growing an intermediate layer on the first substrate comprises depositing an intermediate layer on the first substrate.

15. A method comprising:

forming a cavity in a first substrate;

depositing an intermediate layer on the first substrate after forming the cavity;

securing a second substrate to the intermediate layer;

forming a microelectromechanical structure in a portion of the second substrate;

securing a third substrate to the second substrate to encapsulate the microelectromechanical structure; and

wherein forming the microelectromechanical structure in the portion of the second substrate comprises forming the microelectromechanical structure in the portion of the second substrate before securing the second substrate to the intermediate layer.

16. The method of claim 15 wherein the third substrate comprises carbon, polycrystalline silicon, monocrystalline silicon, amorphous silicon, silicon carbide, silicon/germanium, germanium, or gallium arsenide.

17. The method of claim 15 wherein securing a third substrate to the second substrate comprises bonding a third substrate to the second substrate.

18. The method of claim 15 wherein securing a third substrate to the second substrate comprises fusion bonding and/or anodic-like bonding a third substrate to the second substrate.

23. The method of claim 15 wherein a surface of the third substrate forms a wall of the chamber.

24. The method of claim 15 further comprising forming a cavity in the third substrate, wherein the cavity in the third substrate forms a portion of the chamber.

19. A method comprising:

forming a cavity in a first substrate;

depositing an intermediate layer on the first substrate after forming the cavity;

securing a second substrate to the intermediate layer;

forming a microelectromechanical structure in a portion of the second substrate;

securing a third substrate to the second substrate to encapsulate the microelectromechanical structure;

forming a contact wherein (i) a first portion of the contact is formed from a portion of the second substrate and (ii) a second portion of the contact is formed from a portion of the third substrate;

wherein the first portion of the contact is a semiconductor material having a first conductivity, the third substrate is a semiconductor material having a second conductivity, and the second portion of the contact is a semiconductor material having the first conductivity;

wherein the second portion of the contact is a polycrystalline or monocrystalline silicon that is counterdoped to include the first conductivity; and

further comprising forming a trench around at least a portion of the second portion of the contact.

20. The method of claim 19 wherein the trench includes a first material disposed therein to electrically isolate the second portion of the contact from the third substrate.

21. The method of claim 20 wherein the first material is an insulator material.

22. The method of claim 19 wherein the third substrate is a semiconductor material having a first conductivity and the trench is (i) a semiconductor material having a second conductivity or (ii) an insulation material.