Thin film transistor array substrate, organic light emitting display device comprising the same, and method of manufacturing the same

• US 8,872,165 B2
• Filed: 05/25/2012
• Issued: 10/28/2014
• Est. Priority Date: 11/18/2011
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: You, Chun-Gi, Choi, Joon-Hoo
• Primary Examiner(s): Diaz, Jose R
• Application Number:
  US13/480,746
• Publication Number:
  US 20130126882A1
• Time in Patent Office: 886 Days
• Field of Search: 257/40, 257/59, 257/72, 257/E33.003, 438/34, 438 29- 30, 313/500, 313/505
• US Class Current: 257/40
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H10K 50/81 Anodes
• CPC Class Codes: H10K 50/816 Multilayers, e.g. transparent multilayers
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/121 characterised by the geometry or disposition of pixel elements
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/80517 Multilayers, e.g. transparent multilayers

Abstract

A thin film transistor array substrate includes a thin film transistor including an activation layer, a gate electrode, source and drain electrodes, a first insulation layer between the activation layer and the gate electrode, and a second insulation layer between the gate electrode and the source and drain electrodes, a pixel electrode including a transparent conductive oxide, the pixel electrode being on a portion of the first insulation layer extending from the thin film transistor and being connected to one of the source and drain electrodes via an opening in the second insulation layer, a capacitor including a first electrode and a second electrode, the first electrode being on a same layer as the activation layer and including a transparent conductive oxide, and the second electrode being between the first and second insulation layers, and a third insulation layer covering the source and drain electrodes and exposing the pixel electrode.

Claims

1. A thin film transistor array substrate, comprising:

a thin film transistor including an activation layer, a gate electrode, source and drain electrodes, a first insulation layer between the activation layer and the gate electrode, and a second insulation layer between the gate electrode and the source and drain electrodes;

a pixel electrode including a transparent conductive oxide, the pixel electrode being on a portion of the first insulation layer extending from the thin film transistor, and the pixel electrode being connected to one of the source and drain electrodes via an opening in the second insulation layer;

a capacitor including a first electrode and a second electrode, the first electrode being on a same layer as the activation layer and including a semiconductor doped with ion impurities, the second electrode being between the first and second insulation layers and including a transparent conductive oxide;

a third insulation layer covering the source and drain electrodes and exposing the pixel electrode; and

a connection portion connected to the first electrode, the connection portion disposed on a same layer as the first electrode, wherein the semiconductor doped with ion impurities is present continuously between the first electrode and the connection portion.

2. The thin film transistor array substrate of claim 1, wherein the transparent conductive oxide includes at least one of indium tin oxide, indium zinc oxide, zinc oxid, indium oxide, indium gallium oxide, and aluminum zinc oxide.

3. The thin film transistor array substrate of claim 1, wherein the gate electrode directly contacts the first insulation layer.

4. The thin film transistor array substrate of claim 1, wherein the gate electrode includes a first layer including molybdenum (Mo), a second layer including aluminum (Al), and a third layer including molybdenum (Mo).

5. The thin film transistor array substrate of claim 1, further comprising a signal wiring on a same layer as the gate electrode and formed of a same material as the gate electrode, the signal wiring directly contacting the first insulation layer.

6. The thin film transistor array substrate of claim 1, wherein the pixel electrode further includes a semi-transmitting metal layer.

7. The thin film transistor array substrate of claim 6, wherein the semi-transmitting metal layer is between layers of the transparent conductive oxide.

8. The thin film transistor array substrate of claim 1, wherein a gap exists between the pixel electrode and the second insulation layer.

9. The thin film transistor array substrate of claim 1, wherein the pixel electrode and one of the source and drain electrodes are connected through a layer including a same material as the gate electrode.

10. The thin film transistor array substrate of claim 1, wherein the second electrode and the second insulation layer directly contact each other.

11. An organic light emitting display device, comprising:

a thin film transistor including an activation layer, a gate electrode, source and drain electrodes, a first insulation layer between the activation layer and the gate electrode, and a second insulation layer between the gate electrode and the source and drain electrodes;

a pixel electrode including a transparent conductive oxide, the pixel electrode being on a portion of the first insulation layer extending from the thin film transistor, and the pixel electrode being connected to one of the source and drain electrodes via an opening in the second insulation layer;

a capacitor including a first electrode and a second electrode, the first electrode being on a same layer as the activation layer and including a semiconductor doped with ion impurities, and the second electrode being between the first and second insulation layers and including a transparent conductive oxide;

a third insulation layer covering the source and drain electrodes and exposing the pixel electrode;

an organic light emitting layer on the pixel electrode;

an opposed electrode on the organic light emitting layer; and

a connection portion connected to the first electrode, the connection portion disposed on a same layer as the first electrode, wherein the semiconductor doped with ion impurities is present continuously between the first electrode and the connection portion.

12. The organic light emitting display device of claim 11, wherein the opposed electrode is a reflection electrode for reflecting light irradiated from the organic light emitting layer.

13. A method of manufacturing a thin film transistor array substrate, the method comprising:

a first mask process of forming a semiconductor layer on a substrate and forming an activation layer of a thin film transistor and a first electrode of a capacitor by patterning the semiconductor layer;

a second mask process of forming a first insulation layer, forming a transparent conductive oxide layer on the first insulation layer, and forming a pixel electrode and a second electrode of a capacitor by patterning the transparent conductive oxide layer;

a third mask process of forming a first metal layer, forming a gate electrode of a thin film transistor, and forming a metal connection layer on the pixel electrode;

a fourth mask process of forming a second insulation layer, forming a source area and a drain area of the activation layer on the second insulation layer, and forming an opening for exposing the pixel electrode;

a fifth mask process of forming a second metal layer and forming a source electrode and a drain electrode connected to the source area and the drain area by patterning the second metal layer; and

a sixth mask process of forming a third insulation layer and removing the third insulation layer to expose the pixel electrode;

wherein the first mask process further forms a connection portion connected to the first electrode and, after the third mask process, ion impurities are doped in the source area and the drain area, the first electrode, and the connection portion connected to the first electrode.

14. The method of claim 13, wherein, in the third mask process, the gate electrode is formed to directly contact the first insulation layer.

15. The method of claim 13, wherein, in the fourth mask process, a gap is formed between the second insulation layer and the pixel electrode.

16. The method of claim 13, wherein, in the fifth mask process, the metal connection layer on the pixel electrode is removed.

17. The method of claim 16, wherein the fifth mask process includes a first etching process that etches the second metal layer and a second etching process that etches the metal connection layer.