Embedded source/drains with epitaxial oxide underlayer

• US 8,872,172 B2
• Filed: 10/16/2012
• Issued: 10/28/2014
• Est. Priority Date: 10/16/2012
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Khakifirooz, Ali, Reznicek, Alexander, Sreenivasan, Raghavasimhan, Adam, Thomas N.
• Primary Examiner(s): Luu, Chuong A
• Assistant Examiner(s): FORTICH, RODOLFO D
• Application Number:
  US13/652,521
• Publication Number:
  US 20140103331A1
• Time in Patent Office: 742 Days
• Field of Search: 257/43, 257/266, 257/288, 257/192, 257/E21.09
• US Class Current: 257/43
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Semiconductor structures having embedded source/drains with oxide underlayers and methods for forming the same. Embodiments include semiconductor structures having a channel in a substrate, and a source/drain region adjacent to the channel including an embedded oxide region and an embedded semiconductor region located above the embedded oxide region. Embodiments further include methods of forming a transistor structure including forming a gate on a substrate, etching a source/drain recess in the substrate, filling a bottom portion of the source/drain recess with an oxide layer, and filling a portion of the source/drain recess not filled by the oxide layer with a semiconductor layer.

Claims

1. A semiconductor structure comprising:

a substrate;

a channel region in the substrate; and

a bi-layer source/drain region including an embedded oxide region in the substrate and an embedded semiconductor region above the embedded oxide region

wherein the embedded oxide region comprises cadmium oxide, yttrium oxide, scandium oxide, cerium oxide, lanthanum oxide, praseodymium oxide, thorium oxide, or actinium oxide.

2. The structure of claim 1, wherein the embedded oxide region comprises an epitaxial oxide.

3. The structure of claim 1, wherein the embedded oxide region has approximately the same lattice constant as the embedded semiconductor region.

4. The structure of claim 1, wherein the embedded semiconductor region has a thickness within the substrate of about 5 nm to about 10 nm.

5. The structure of claim 1, wherein the thickness of the embedded semiconductor region comprises about 5% to about 12.5% of the thickness of the source/drain region.

6. The structure of claim 1, wherein the embedded oxide region has a thickness of about 70 nm to about 95 nm.

7. The structure of claim 1, wherein the thickness of the embedded oxide region comprises about 87.5% to about 95% of the thickness of the source/drain region.

8. The structure of claim 1, wherein a top surface of the source/drain region is above a top surface of the substrate.

9. The structure of claim 1, wherein the embedded semiconductor region comprises a silicon-germanium alloy or a silicon-carbon alloy.

10. The structure of claim 1, further comprising:

a gate on the semiconductor substrate above the channel region; and

a spacer on a sidewall of the gate, wherein the spacer laterally offsets the source/drain region from the gate.

11. A method of forming a transistor structure, the method comprising:

etching a source/drain recess in a semiconductor substrate;

forming an embedded oxide region in a portion of the source/drain recess; and

forming an embedded semiconductor region in the source/drain recess above the embedded oxide region,

wherein forming an embedded oxide region in the portion of the source/drain recess comprises growing an epitaxial oxide in a bottom portion of the source/drain recess;

wherein the epitaxial oxide is a rare-earth oxide selected from the group consisting of cadmium oxide, yttrium oxide, scandium oxide, cerium oxide, lanthanum oxide, praseodymium oxide, thorium oxide, and actinium oxide.

12. The method of claim 11, wherein forming an embedded semiconductor region above the embedded oxide region comprises epitaxially growing a silicon-germanium alloy or a silicon-carbon alloy on the embedded oxide region.

13. The method of claim 11, further comprising forming a spacer on a sidewall of a gate, wherein the source/drain recess is laterally offset from the gate by the spacer.

14. A method of forming a source/drain region, the method comprising:

selecting a desired amount of stress to be applied by the source/drain region;

selecting a semiconductor material that will apply the desired amount of stress when formed in the source/drain region;

selecting a oxide with a similar lattice constant as the semiconductor material;

forming a source/drain recess having a top portion and a bottom portion in a substrate;

forming the oxide in the bottom portion of the source/drain recess; and

forming the semiconductor material on the oxide at least partially in the top portion of the source/drain recess,

wherein the oxide comprises a rare-earth oxide selected from the group consisting of cadmium oxide, yttrium oxide, scandium oxide, cerium oxide, lanthanum oxide, praseodymium oxide, thorium oxide, and actinium oxide.

15. The method of claim 14, wherein the semiconductor material is a silicon-germanium alloy or a silicon-carbon alloy.

16. The method of claim 15 wherein the semiconductor material comprises a silicon-germanium alloy with a germanium concentration of about 25% to about 50%.

17. The method of claim 15, wherein the semiconductor material comprises a silicon-carbon alloy with a carbon concentration of about 0.5% to about 2%.