Contact structure employing a self-aligned gate cap

• US 8,872,244 B1
• Filed: 04/18/2013
• Issued: 10/28/2014
• Est. Priority Date: 04/18/2013
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: He, Hong, Tseng, Chiahsun, Yeh, Chun-chen, Yin, Yunpeng
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Parker, John M
• Application Number:
  US13/865,512
• Publication Number:
  US 20140312433A1
• Time in Patent Office: 558 Days
• Field of Search: 257/410, 257/412, 257/750, 257/751, 257/211, 257/288, 438/592, 438/595, 438/652, 438/655
• US Class Current: 257/288
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion.

Claims

1. A semiconductor structure comprising:

a gate structure including a stack of a gate dielectric and a gate electrode and overlying a portion of a semiconductor material layer;

a first dielectric material layer comprising a first dielectric material and overlying said semiconductor material layer;

a second dielectric material layer comprising a second dielectric material that is different from said first dielectric material and overlying said first dielectric material layer and including a planar top surface;

a gate cap dielectric material portion comprising at least a third dielectric material that is different from said first and second dielectric materials and overlying said gate structure and contacting sidewalls of said first dielectric material layer; and

a contact via structure extending through said second and first dielectric material layers, providing electrical contact to an element in said semiconductor material layer, and contacting at least a sidewall of said gate cap dielectric material portion,

wherein said gate cap dielectric material portion comprises;

a third dielectric material portion comprising said third dielectric material and contacting said sidewalls of said first dielectric material layer; and

a dielectric stack of a fourth dielectric material portion and a fifth dielectric material portion, wherein said dielectric stack is laterally surrounded by said third dielectric material portion.

2. The semiconductor structure of claim 1, wherein outer sidewalls of said gate cap dielectric material portion are laterally offset outward from outer sidewalls of said gate structure by a same offset distance throughout an entire periphery of said gate structure.

3. The semiconductor structure of claim 1, wherein said third dielectric material comprises a dielectric metal oxide.

4. The semiconductor structure of claim 1, wherein each of said third dielectric material portion and said dielectric stack has a topmost surface that is coplanar with a top surface of said second dielectric material layer.

5. The semiconductor structure of claim 1, further comprising a dielectric liner in contact with all bottom surfaces of said first dielectric material layer and overlying said semiconductor material layer and said gate structure.

6. The semiconductor structure of claim 5, further comprising a gate spacer comprising a dielectric material and laterally surrounding said gate structure, wherein outer sidewalls of said gate spacer contact said dielectric liner.

7. The semiconductor structure of claim 1, wherein said contact via structure overlies a peripheral portion of said gate cap dielectric material portion.

8. The semiconductor structure of claim 7, wherein said contact via structure contacts a surface of said gate cap dielectric material portion that is recesses relative a topmost horizontal surface of said gate cap dielectric material portion.

9. The semiconductor structure of claim 1, wherein said element in said semiconductor material layer is a source region or a drain region of a field effect transistor.