Integrated gate runner and field implant termination for trench devices

• US 8,872,278 B2
• Filed: 10/25/2011
• Issued: 10/28/2014
• Est. Priority Date: 10/25/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Hao, Jifa, Dolny, Gary, Rioux, Mark
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): Ahmad, Khaja
• Application Number:
  US13/280,452
• Publication Number:
  US 20130099311A1
• Time in Patent Office: 1,099 Days
• Field of Search: 257/287, 257/341, 257/409, 257/488, 257492-493, 257/E29.13, 257/E29.257, 257/E29.201, 257/E21.418, 257/E21.545
• US Class Current: 257/401
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one general aspect, an apparatus can include a plurality of trench metal-oxide-semiconductor field effect transistors (MOSFET) devices formed within an epitaxial layer of a substrate, and a gate-runner trench disposed around the plurality of trench MOSFET devices and disposed within the epitaxial layer. The apparatus can also include a floating-field implant defined by a well implant and disposed around the gate-runner trench.

Claims

1. An apparatus, comprising:

a plurality of trench metal-oxide-semiconductor field effect transistors (MOSFET) devices formed within an epitaxial layer of a substrate;

a gate-runner trench disposed around the plurality of trench MOSFET devices and disposed within the epitaxial layer, the gate-runner trench being continuous;

a floating-field implant defined by a well implant and disposed around the gate-runner trench, the floating-field implant having a bottom interface and at least one side interface in direct contact with the epitaxial layer, the floating-field implant defining a pn-junction with the epitaxial layer; and

a polysilicon material disposed within the gate-runner trench and at least one device trench of the plurality of trench MOSFET devices, the polysilicon material being in contact with the epitaxial layer and an active area implant that is disposed in the substrate.

2. The apparatus of claim 1, wherein the floating-field implant is a first floating-field implant and the well implant is a first well implant,

the apparatus further comprising:

a second floating-field implant defined by a second well implant, the second floating-field implant being disposed around the gate-runner trench and around the first floating-field implant.

3. The apparatus of claim 1, wherein the polysilicon material includes a recessed portion, the apparatus further comprising:

a metallic material disposed within the recessed portion of the polysilicon material.

4. The apparatus of claim 1, wherein the gate-runner trench is a first gate-runner trench,

the apparatus further comprising:

a second gate-runner trench disposed around the plurality of trench MOSFET devices; and

a metallic material disposed over the first gate-runner trench and the second gate-runner trench.

5. The apparatus of claim 1, wherein the gate-runner trench is a first gate-runner trench,

the apparatus further comprising:

a second gate-runner trench disposed around the plurality of trench MOSFET devices; and

a metallic material configured to electrically couple a first conductive material disposed within the first gate-runner trench and a second conductive material disposed within the second gate-runner trench.

6. The apparatus of claim 1, wherein the gate-runner trench and the floating-field implant collectively function as a termination for an edge trench MOSFET device from the plurality of trench MOSFET devices.

7. The apparatus of claim 1, further comprising:

a gate electrode coupled to a trench MOSFET device from the plurality of trench MOSFET devices; and

an electrically conductive material disposed within the gate-runner trench and electrically coupled to the gate electrode.

8. An apparatus, comprising:

a plurality of trench semiconductor devices formed within an epitaxial layer of a substrate;

a gate-runner trench disposed around the plurality of trench semiconductor devices and disposed within the epitaxial layer, the gate-runner trench being continuous and completely surrounding the plurality of trench semiconductor devices;

a polysilicon material disposed within the gate-runner trench and at least one device trench of the plurality of trench semiconductor devices, the polysilicon material having a recessed portion in the gate runner trench and being in contact with the epitaxial layer and an active area implant that is disposed in the substrate.

9. The apparatus of claim 8, further comprising:

a metallic material disposed within the recessed portion of the polysilicon material, the metallic material defining a gate runner.

10. The apparatus of claim 8, further comprising:

a floating-field implant defined by a well implant and disposed around the gate-runner trench.

11. The apparatus of claim 8, further comprising:

a plurality of floating-field implants each defined by a well implant and each disposed around the gate-runner trench.

12. The apparatus of claim 8, wherein the gate-runner trench is first gate-runner trench,

the apparatus further comprising:

a second gate-runner trench disposed around the plurality of trench semiconductor devices; and

a metallic material disposed over the first gate-runner trench and the second gate-runner trench.

13. The apparatus of claim 8, further comprising:

a device trench included in a trench MOSFET device from the plurality of trench MOSFET devices, the device trench having at least one of a depth different from a depth of the gate-runner trench or a width different from a width of the gate-runner trench.

14. The apparatus of claim 8, further comprising:

a floating-field implant defined within the epitaxial layer and disposed around the gate-runner trench, the floating-field implant having a dopant concentration different from a dopant concentration of at least one of the plurality of trench semiconductor devices.

15. An apparatus, comprising:

a first doped region within a floating-field region of an epitaxial layer of a substrate, the first doped region having a bottom interface and at least one side interface in direct contact with the epitaxial layer, the first doped region defining a pn-junction with the epitaxial layer;

at least a portion of a second doped region disposed within an active region of the epitaxial layer;

a continuous gate-runner trench disposed within a gate-runner region of the epitaxial layer, the gate-runner region of the epitaxial layer being disposed between the active region of the epitaxial layer and the floating-field region of the epitaxial layer; and

a polysilicon material disposed within the continuous gate-runner trench and at least one device trench that is disposed in the substrate, the polysilicon material being in contact with the epitaxial layer and an active area implant disposed in the substrate.

16. The apparatus of claim 15, wherein the first doped region and the second doped region are formed using a same implant process.

17. The apparatus of claim 15, further comprising:

a recess disposed within the polysilicon material in the gate-runner trench; and

a metallic material disposed within the recess.

18. The apparatus of claim 15, wherein the first doped region has a first dopant concentration different from a dopant concentration of the second doped region.