Integrated structure for MEMS device and semiconductor device and method of fabricating the same
First Claim
1. An integrated structure for a MEMS device and a semiconductor device, comprising:
- a substrate;
a dielectric layer formed on the substrate;
a MEMS device formed in the substrate or in or partially in the dielectric layer and exposed to the environment;
a semiconductor device formed in or partially in the substrate or in or partially in the dielectric layer;
an etch stopping element formed on the substrate and in or partially in the dielectric layer between the MEMS device and the semiconductor device, surrounding the MEMS device on all sides of the MEMS device in a plane parallel to the substrate, and not covering the MEMS device, and further comprising an etch-resistant material layer stacked with etch-resistant material plugs, thereby to protect the semiconductor device from being etched during a release process for making the MEMS device;
an interconnect having a plurality of layers disposed within the dielectric layer and contacting the semiconductor device, wherein a top layer of the interconnect is on the dielectric layer; and
a passivation layer covering the top layer of the interconnect and not covering the MEMS device.
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Accused Products
Abstract
The present invention relates to an integrated structure for a MEMS device and a semiconductor device and a method of fabricating the same, in which an etch stopping element is included on a substrate between the MEMS device and the semiconductor device for protecting the semiconductor device from lateral damage when an oxide releasing process is performed to fabricate the MEMS device. The etch stopping element has various profiles and is selectively formed by an individual fabricating process or is simultaneously formed with the semiconductor device in the same fabricating process. It is a singular structure or a combined stacked multilayered structure, for example, a plurality of rows of pillared etch-resistant material plugs, one or a plurality of wall-shaped etch-resistant material plugs, or a multilayered structure of a stack of which and an etch-resistant material layer.
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Citations
19 Claims
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1. An integrated structure for a MEMS device and a semiconductor device, comprising:
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a substrate; a dielectric layer formed on the substrate; a MEMS device formed in the substrate or in or partially in the dielectric layer and exposed to the environment; a semiconductor device formed in or partially in the substrate or in or partially in the dielectric layer; an etch stopping element formed on the substrate and in or partially in the dielectric layer between the MEMS device and the semiconductor device, surrounding the MEMS device on all sides of the MEMS device in a plane parallel to the substrate, and not covering the MEMS device, and further comprising an etch-resistant material layer stacked with etch-resistant material plugs, thereby to protect the semiconductor device from being etched during a release process for making the MEMS device; an interconnect having a plurality of layers disposed within the dielectric layer and contacting the semiconductor device, wherein a top layer of the interconnect is on the dielectric layer; and a passivation layer covering the top layer of the interconnect and not covering the MEMS device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 16, 17)
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11. An integrated structure for a MEMS device and a semiconductor device, comprising:
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a substrate; a dielectric layer formed on the substrate; a MEMS device formed in the substrate or in or partially in the dielectric layer and exposed to the environment; a semiconductor device formed in or partially in the substrate or in or partially in the dielectric layer; and a metal layer or a polysilicon layer stacked with metal plugs or polysilicon plugs, formed on the substrate and in or partially in the dielectric layer between the MEMS device and the semiconductor device, surrounding the MEMS device on all sides of the MEMS device in a plane parallel to the substrate, and not covering the MEMS device, thereby to protect the semiconductor device from being etched during a release process for making the MEMS device; an interconnect having a plurality of layers disposed within the dielectric layer and contacting the semiconductor device, wherein a top layer of the interconnect is on the dielectric layer; and a passivation layer covering the top layer of the interconnect and not covering the MEMS device. - View Dependent Claims (12, 13, 14, 15, 18, 19)
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Specification