Forming grounded through-silicon vias in a semiconductor substrate

• US 8,872,345 B2
• Filed: 07/07/2011
• Issued: 10/28/2014
• Est. Priority Date: 07/07/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Wei-Cheng, Yen, Hsiao-Tsung, Hu, Hsien-Pin, Hou, Shang-Yun, Jeng, Shin-Puu, Hsieh, Chi-Chun
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US13/178,079
• Publication Number:
  US 20130009317A1
• Time in Patent Office: 1,209 Days
• Field of Search: 257/415, 257/E29.324, 257/E21.002, 257685-686, 257750-751, 257773-774, 257/777, 257/E23.085, 438/50
• US Class Current: 257/774
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILD layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.

Claims

1. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate, the semiconductor substrate having a first side and a second side opposite the first side;

forming a through-silicon via (TSV) opening extending from the first side of the semiconductor substrate into the semiconductor substrate;

forming a liner layer on the first side of the semiconductor substrate and along the sidewalls and bottom of the TSV opening;

depositing a first conductive material layer over the liner layer in the opening to form a TSV;

forming an inter-layer dielectric (ILD) layer over the first side of the semiconductor substrate;

forming a via opening extending from the ILD layer into a portion of the semiconductor substrate;

forming a trench opening in the ILD layer to expose a portion of the TSV; and

depositing a second conductive material layer in the via and the trench openings to form an interconnect structure, the interconnect structure electrically connecting the TSV with the semiconductor substrate.

2. The method of claim 1, wherein the semiconductor device is an interposer.

3. The method of claim 1, after the forming the TSV, further comprising planarizing the first side of the semiconductor substrate.

4. The method of claim 1, further comprising forming a first barrier layer between the liner layer and the TSV.

5. The method of claim 4, further comprising forming a first seed layer between the first barrier layer and the TSV.

6. The method of claim 1, before the forming the ILD layer over the first side of the semiconductor substrate, further comprising forming an etch stop layer.

7. The method of claim 1, further comprising forming a second barrier layer over the via and trench openings.

8. The method of claim 7, further comprising forming a second seed layer over the second barrier layer.

9. The method of claim 1, wherein the interconnect structure is formed by electro-chemical plating.

10. The method of claim 1, wherein the TSV and interconnect structure comprise copper or copper alloys.

11. The method of claim 1, after the forming the interconnect structure, further comprising planarizing the first side of the semiconductor substrate.

12. A method of forming an interposer, comprising:

providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface;

forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate;

forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and

forming an interconnect structure having a first partition and a second partition, the first partition formed in the ILD layer and the second partition formed in a portion of the semiconductor substrate, wherein the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.

13. The method of claim 12, further comprising forming a liner layer between at least the one or more TSVs and the semiconductor substrate.

14. The method of claim 13, further comprising forming a barrier layer and/or a seed layer between the one or more TSVs and the liner layer.

15. The method of claim 12, further comprising forming a barrier layer and/or seed layer between at least the interconnect structure and the ILD layer and the front surface of the semiconductor substrate.

16. An integrated circuit structure, comprising:

a semiconductor substrate having a front surface and a back surface opposite the front surface;

a through-silicon via (TSV) formed extending from the front surface of the semiconductor substrate into the semiconductor substrate; and

an interconnect structure having a first partition and a second partition, the first partition formed in an inter-layer dielectric (ILD) layer, the ILD layer overlying the front surface of the semiconductor substrate, and the second partition formed in a portion of the semiconductor substrate, wherein the interconnect structure electrically connects the TSV to the semiconductor substrate.

17. The integrated circuit structure of claim 16, wherein the integrated circuit structure is an interposer.

18. The integrated circuit structure of claim 16, further comprising a liner layer formed at least between the TSV and the semiconductor substrate.

19. The integrated circuit structure of claim 18, further comprising:

a barrier layer formed between the TSV and the liner layer; and

a seed layer formed between the TSV and the barrier layer.

20. The integrated circuit structure of claim 16, wherein the interconnect structure and the TSV are formed of the same conductive material.

21. The integrated circuit structure of claim 17, wherein the interposer comprises passive devices.

22. The integrated circuit structure of claim 21, wherein the interposer comprises active devices.

23. An interposer, comprising:

a semiconductor substrate having a front surface and a back surface opposite the front surface;

a through-silicon via (TSV) formed extending from the front surface of the semiconductor substrate into the semiconductor substrate;

a liner layer formed at least between the TSV and the semiconductor substrate;

an inter-layer dielectric (ILD) layer formed over the front surface of the semiconductor substrate; and

an interconnect structure having a first partition and a second partition, the first partition formed in the ILD layer and the second partition formed in a portion of the semiconductor substrate, wherein the interconnect structure electrically connects the TSV to the semiconductor substrate.

24. The interposer of claim 23, further comprising a barrier layer formed between the TSV and the liner layer.

25. The interposer of claim 24, further comprising a seed layer formed between the TSV and the barrier layer.

26. The interposer of claim 23, wherein the interconnect structure and the TSV are formed of the same conductive material.

27. The interposer of claim 23, further comprising passive devices.

28. The interposer of claim 27, further comprising active devices.

29. A semiconductor package structure, comprising:

an interposer having;

a semiconductor substrate having a front surface and a back surface opposite the front surface;

a through-silicon via (TSV) formed extending from the front surface of the semiconductor substrate into the semiconductor substrate;

a liner layer formed at least between the TSV and the semiconductor substrate;

an inter-layer dielectric (ILD) layer formed over the front surface of the semiconductor substrate; and

an interconnect structure having a first partition and a second partition, the first partition formed in the ILD layer and the second partition formed in a portion of the semiconductor substrate, wherein the interconnect structure electrically connects the TSV to the semiconductor substrate;

a semiconductor chip; and

a plurality of bonding pads bonding the semiconductor chip to the interposer.

30. The semiconductor package structure of claim 29, further comprising an additional semiconductor chip bonded onto the semiconductor chip.

31. The semiconductor package structure of claim 29, wherein the interposer comprises passive devices.

32. The semiconductor package structure of claim 31, wherein the interposer further comprises active devices.

33. A semiconductor package structure, comprising:

an interposer having;

a semiconductor substrate having a front surface and a back surface opposite the front surface;

a through-silicon via (TSV) formed extending from the front surface of the semiconductor substrate into the semiconductor substrate;

a liner layer formed at least between the TSV and the semiconductor substrate;

an inter-layer dielectric (ILD) layer formed over the front surface of the semiconductor substrate; and

an interconnect structure having a first partition and a second partition, the first partition formed in the ILD layer and the second partition formed in a portion of the semiconductor substrate, wherein the interconnect structure electrically connects the TSV to the semiconductor substrate;

a multi-chip semiconductor structure having at least a first chip and a second chip; and

a plurality of bonding pads bonding the multi-chip semiconductor structure to the interposer.

34. The semiconductor package structure of claim 33, wherein the interposer comprises passive devices.

35. The semiconductor package structure of claim 34, wherein the interposer further comprises active devices.