Characterizing dies

• US 8,872,536 B1
• Filed: 03/22/2011
• Issued: 10/28/2014
• Est. Priority Date: 03/22/2011
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Trimberger, Stephen M., Ehteshami, Babak
• Primary Examiner(s): Koval, Melissa
• Assistant Examiner(s): MCDONNOUGH, COURTNEY G
• Application Number:
  US13/069,319
• Time in Patent Office: 1,316 Days
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

An embodiment of a method to characterize a die is disclosed. The embodiment of the method includes measuring a quality metric of the die, and determining, prior to a final test stage, whether the quality metric of the die satisfies a first constraint, where the first constraint is more stringent than a second constraint at the final test stage for the quality metric of the die.

Claims

1. A method to characterize a die, comprising:

measuring a quality metric of the die during a wafer sort stage;

determining, prior to a final test stage, whether the quality metric of the die satisfies a first constraint, wherein the first constraint is more stringent than a second constraint at the final test stage for the quality metric of the die;

selecting a die to be packaged based upon the measuring of the quality metric of the die during the wafer sort stage;

establishing that the packaged die satisfies the second constraint at the final test stage based upon the determination that the die satisfies the first constraint during the wafer sort stage.

2. The method of claim 1, wherein the measuring the quality metric of the die comprises measuring at least one of:

(a) a performance, (b) a power consumption, (c) a functionality, (d) a single event upset (SEU) immunity, (e) a random defect rate, (f) a capacitance measure, (g) a functional yield, and (h) a number of repaired defects of the die, and

wherein the determining, prior to the final test stage, whether the quality metric of the die satisfies the first constraint comprises determining, prior to the final test stage, whether at least one of the following satisfies the first constraint;

(a) the performance, (b) the power consumption, (c) the functionality, (d) the SEU immunity, (e) the random defect rate, (f) the capacitance measure, (g) the functional yield, and (h) the number of repaired defects of the die.

3. The method of claim 2, wherein the die is a programmable logic device (PLD) comprising a plurality of configuration logic blocks (CLBs), and wherein measuring the quality metric of the die comprises measuring the performance of the PLD by:

configuring a first portion of the plurality of CLBs as an oscillator;

configuring a second portion of the plurality of CLBs as a counter;

generating, by the oscillator, a clock signal;

transmitting the clock signal to a clock input of the counter; and

generating, by the counter, a count value.

4. The method of claim 3, wherein determining, prior to the final test stage, whether the quality metric of the die satisfies the first constraint comprises determining, prior to the final test stage, whether the performance of the PLD satisfies the first constraint by:

configuring a third portion of the plurality of CLBs as a threshold comparator;

determining, using the threshold comparator, whether the count value is greater than a first threshold count value; and

generating a pass value to indicate whether the count value is greater than the first threshold count value, wherein the first threshold count value is greater than a second threshold count value at the final test stage.

5. The method of claim 2, wherein the die is a processor, and wherein measuring the quality metric of the die comprises measuring the performance of the processor by:

running the processor at a clock rate that is faster than another clock rate at which the processor runs at the final test stage; and

executing a test routine on the processor running at the first clock rate.

6. The method of claim 5, wherein determining, prior to the final test stage, whether the quality metric of the die satisfies the first constraint comprises determining, prior to the final test stage, whether the performance of the processor satisfies the first constraint by:

determining whether the test routine executed by the processor running at the first clock rate produced a correct result, wherein the first clock rate is faster than a second clock rate at which the processor runs at the final test stage; and

generating a pass value to indicate whether the test routine executed by the processor running at the first clock rate produced the correct result.

7. The method of claim 2, wherein the die is a PLD comprising a plurality of CLBs, and wherein measuring the quality metric of the die comprises measuring the power consumption of the die by:

configuring a portion of the plurality of CLBs; and

measuring the power consumption when configuring the portion of the plurality of CLBs.

8. The method of claim 2, wherein the die is a processor, and wherein measuring the quality metric of the die comprises measuring the power consumption of the processor by:

loading a test routine into the processor;

executing the test routine; and

measuring the power consumption when executing the test routine.

9. The method of claim 3, further comprising:

generating a rank value based on the count value;

storing, in a wafer map, the rank value corresponding to the die;

after a wafer sort stage, retrieving, from the wafer map, the rank value corresponding to the die; and

determining whether to package the die based on the rank value corresponding to the die.

10. The method of claim 2, wherein measuring the quality metric of the die comprises measuring the functionality of the die by:

measuring at least one of an amount of usable memory on the die, a number of functional processors on the die, and a number of functional processors on the die that satisfy a functional processor constraint,

and wherein determining, prior to the final test stage, whether the quality metric of the die satisfies the first constraint comprises determining, prior to the final test stage, whether the functionality of the die satisfies the first constraint by;

determining at least one of;

whether the amount of usable memory on the die is greater than a first threshold usable memory value, whether the number of functional processors on the die is greater than a first threshold number of functional processors, and whether the number of functional processors on the die that satisfy the functional processor constraint is greater than a first threshold number of satisfying functional processors,

wherein the first threshold usable memory value is greater than a second threshold usable memory value at the final test stage, the first threshold number of functional processors is greater than a second threshold number of functional processors at the final test stage, and the first threshold number of satisfying functional processors is greater than a second threshold number of satisfying functional processors at the final test stage.

11. A device, comprising:

a measuring unit to measure a quality metric of a die during a wafer sort stage; and

a characteristic checking unit, coupled to the measuring unit, to determine, prior to a final test stage, whether the quality metric of the die satisfies a first constraint, wherein the first constraint is more stringent than a second constraint at the final test stage for the quality metric of the die, and the die is established as satisfying the second constraint as a packaged die at the final test stage if the die satisfies the first constraint during the wafer sort stage.

12. The device of claim 11, wherein the device is within the die, and the die is a PLD comprising a plurality of CLBs, and

wherein the measuring unit comprises:

a first portion of the plurality of CLBs configured as an oscillator to generate a clock signal, and

a second portion of the plurality of CLBs configured as a counter to generate a count value based on the clock signal, and

wherein the characteristic checking unit comprises;

a third portion of the plurality of CLBs configured as a threshold comparator, wherein the threshold comparator determines whether the count value is greater than a first threshold count value and the threshold comparator generates a pass value to indicate whether the count value is greater than the first threshold count value, wherein the first constraint is the first threshold count value that is greater than a second threshold count value at the final test stage.

13. The device of claim 11, wherein the device is within the die, and the die is a processor running at a first clock rate, wherein the processor is programmed to implement:

the measuring unit to execute a test routine on the processor running at the first clock rate, wherein the first constraint is the first clock rate at which the processor is running, and the first clock rate is faster than a second clock rate at which the processor runs at the final test stage, and

the characteristic checking unit to determine whether the test routine executed by the processor running at the first clock rate generated a correct result, and the characteristic checking unit generates a pass value to indicate whether the processor running at the first clock rate generated the correct result.

14. The device of claim 11, wherein the device is a test unit, wherein the test unit comprises a processor programmed to implement:

the measuring unit to measure a power consumption of the die by either;

(a) measuring the power consumption when configuring a portion of a plurality of CLBs of the die, or (b) measuring the power consumption when the die executes a test routine, and

the characteristic checking unit to determine, prior to the final test stage, whether the power consumption of the die satisfies the first constraint by determining if the power consumption is less than a first threshold power consumption, and generates a pass value to indicate whether the first power consumption is less than the threshold power consumption, wherein the first constraint is the threshold power consumption which is lower than a second threshold power consumption at the final test stage.

15. A method to reduce inventory costs, comprising:

characterizing a die based on whether a quality metric of the die satisfies a first constraint at a wafer sort stage, wherein the first constraint is more stringent than a second constraint at a final test stage for the quality metric of the die;

establishing that the die will satisfy the second constraint at a final test stage if the die satisfies the first constraint during the wafer sort stage;

dicing a wafer that includes the die;

binning the die based on the quality metric of the die; and

selecting the die from the die bank to be packaged based upon the characterization that the quality metric of the die satisfies the first constraint at the wafer sort stage;

wherein the packaged die is established as satisfying the second constraint at the final test stage if the die satisfies the first constraint during the wafer sort stage.

16. The method of claim 15, further comprising, prior to characterizing the die, measuring the quality metric of the die.

17. The method of claim 16, wherein the measuring the quality metric of the die comprises measuring at least one of:

(a) a performance, (b) a power consumption, (c) a functionality, (d) a SEU immunity, (e) a random defect rate, (f) a capacitance measure, (g) a functional yield, and (h) a number of repaired defects of the die, and

wherein the characterizing the die based on whether the quality metric of the die satisfies the first constraint comprises characterizing the die based on whether at least one of the following satisfies the first constraint;

(a) the performance, (b) the power consumption, (c) the functionality, (d) the SEU immunity, (e) the random defect rate, (f) the capacitance measure, (g) the functional yield, and (h) the number of repaired defects of the die.

18. The method of claim 16, wherein the measuring the quality metric of the die only occurs at the wafer sort stage.

19. The method of claim 17, further comprising, after the die is packaged, measuring the performance only of components of the die whose performance is dependent on packaging.

20. The method of claim 15, further comprising, packaging the die only if the quality metric satisfies the first constraint.