LCD panel with structure of Cs-on-gate type storage capacitor connecting with thin film transistor

• US 8,872,747 B2
• Filed: 08/20/2013
• Issued: 10/28/2014
• Est. Priority Date: 03/17/2009
• Status: Active Grant

• Current Assignee: Wintek Corporation
• Original Assignee: Wintek Corporation
• Inventors: Chen, Yu-Ting, Wang, Hung-Jen
• Primary Examiner(s): Karimi, Pegeman
• Application Number:
  US13/970,668
• Publication Number:
  US 20130335654A1
• Time in Patent Office: 434 Days
• Field of Search: 345/87, 345/90, 345/98, 345/100, 345/204, 345/690, 345/88
• US Class Current: 345/98
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2320/02 Improving the quality of display appearance
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

Abstract

A liquid crystal display (LCD) panel is provided. The LCD panel includes a plurality of pixel units each having a storage capacitor, a plurality of scan lines coupled to the pixel units, and a plurality of storage capacitor charge transistors each respectively coupled to the storage capacitors of the corresponding pixel units and further coupled to two of the scan lines. The storage capacitor charge transistors are used for charging the storage capacitors of the pixel units.

Claims

1. A display panel, comprising:

a pixel array comprising a plurality of pixel units each at least comprising a storage capacitor defined by a pixel electrode and an electrode being disposed along the pixel electrode;

a plurality of scan lines coupled to the pixel units;

a plurality of data lines intersect with the scan lines and coupled to the pixel units; and

a plurality of storage capacitor charge transistors, at least one of the storage capacitor charge transistors comprising;

a first terminal coupled to the storage capacitor of the pixel unit;

a second terminal coupled to an n^th scan line of the scan lines; and

a third terminal coupled to an (n+1)^th scan line of the scan lines, wherein n is an integer equal or larger than 1;

wherein the pixel electrode has a plurality of holes between two of the data lines adjacent to each other, the electrode includes a patterned sheet having a shape conformed with the shape of the holes of the pixel electrode and located right under the holes of the pixel electrode, the storage capacitor charge transistors charge the storage capacitors of the corresponding pixel units with the second scan line of the scan lines only when the first scan line of the scan lines is turn on.

2. The display panel according to claim 1, wherein the storage capacitor comprises:

a first terminal coupled to the first terminal of the storage capacitor charge transistor; and

a second terminal.

3. The display panel according to claim 2,

wherein each pixel unit further comprises:

an active element comprising a first terminal coupled to one of the scan lines, a second terminal coupled to one of the data lines, and a third terminal coupled to the second terminal of the storage capacitor; and

a liquid crystal capacitor comprising a first terminal coupled to the second terminal of the storage capacitor, and a second terminal coupled to a common voltage.

4. The display panel according to claim 3, wherein when the n^th scan line of the scan lines is turned on and maintains at a first potential and the (n+1)_th scan line of the scan lines is turned off and maintains at a second potential, the storage capacitor charge transistor is turned on, so that the first terminal of the storage capacitor maintains at the second potential and the second terminal of the storage capacitor maintains at a potential of one of the data lines.

5. The display panel according to claim 4, wherein when the n^th scan line of the scan lines is turned off and maintains at the second potential and the (n+1)^th scan line of the scan lines is turned on and maintains at the first potential, the storage capacitor charge transistor is turned off, so that the first terminal of the storage capacitor is in floating.

6. The display panel according to claim 1, wherein the opening of the pixel electrode is a hole.

7. A display panel, comprising:

at least one pixel unit comprising at least one storage capacitor defined by a pixel electrode and an electrode being disposed along the pixel electrode, the storage capacitor comprising;

a first terminal; and

a second terminal;

a plurality of scan lines;

a first scan line coupled to the pixel unit;

a second scan line; and

at least one storage capacitor charge transistor comprising a first terminal coupled to the first terminal of the storage capacitor of the pixel unit, a second terminal coupled to the first scan line and a third terminal coupled to the second scan line;

wherein the pixel electrode has a plurality of holes between two of the data lines adjacent to each other, the electrode includes a patterned sheet having a shape conformed with the shape of the holes of the pixel electrode and located right under the holes of the pixel electrode, the storage capacitor charge transistor charges the storage capacitor of the pixel unit with the second scan line only when the first scan line is turn on.

8. The display panel according to claim 7,

wherein the pixel unit further comprises:

an active element comprising a first terminal coupled to the first scan line, a second terminal coupled to one of the data line, and a third terminal coupled to the second terminal of the storage capacitor; and

a liquid crystal capacitor comprising a first terminal coupled to the second terminal of the storage capacitor, and a second terminal coupled to a common voltage.

9. The display panel according to claim 8, wherein when the first scan lines is turned on and maintains at a first potential and the second scan lines is turned off and maintains at a second potential, the storage capacitor charge transistor is turned on, so that the first terminal of the storage capacitor maintains at the second potential and the second terminal of the storage capacitor maintains at a potential of the one of the data line.

10. The display panel according to claim 9, wherein when the first scan lines is turned off and maintains at the second potential and the second scan lines is turned on and maintains at the first potential, the storage capacitor charge transistor is turned off, so that the first terminal of the storage capacitor is in floating.

11. The display panel according to claim 7, wherein the opening of the pixel electrode is a hole.

12. A display panel, comprising:

at least one first active element; and

a plurality of pixel unit each comprising;

a data line;

a scan line;

a pixel electrode having a plurality of holes between the data line and another data line adjacent to the data line;

a second active element having a first terminal coupled to the scan line, a second terminal coupled to the data line, and a third terminal coupled to the pixel electrode; and

an electrode coupled to the at least one first active element, for receiving a scan signal of another scan line through the at least one first active element;

wherein a part of the electrode is coupled to the opening of the pixel electrode, the electrode includes a patterned sheet having a shape conformed with the shape of the holes of the pixel electrode and located right under the holes of the pixel electrode, and a storage capacitor is defined by the electrode and the pixel electrode.

13. The display panel according to claim 12, wherein the opening of the pixel electrode is a hole.