Semiconductor memory apparatus and test circuit therefor

• US 8,873,272 B2
• Filed: 12/30/2011
• Issued: 10/28/2014
• Est. Priority Date: 11/04/2011
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Jae Ung
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): HUERTA, PABLO S
• Application Number:
  US13/340,956
• Publication Number:
  US 20130114326A1
• Time in Patent Office: 1,033 Days
• Field of Search: 365/148
• US Class Current: 365/148
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

Disclosed is a semiconductor memory apparatus, including: a memory cell array configured to include a plurality of memory cells; a switching unit configured to be coupled to data input and output pads and control a data transfer path of data applied to the data input and output pads in response to a test mode signal; a write driver configured to drive data transferred from the switching unit and write the data in the memory cell array at a normal mode; and a controller configured to transfer the data from the switching unit to the memory cell at a test mode.

Claims

1. A semiconductor memory apparatus, comprising:

a memory cell array configured to include a plurality of memory cells;

a switching unit configured to be coupled to a data input buffer through data input and output pads and control a data transfer path of data applied to the data input buffer in response to a test mode signal;

a write driver configured to drive data transferred from the switching unit and write the data in the memory cell array at a normal mode; and

a controller configured to directly transfer the data from the switching unit to the memory cell without passing through the write driver at a test mode,

wherein the memory cell array and the controller are configured to be directly coupled through a first local input and output lines which are substantially connected to bit lines of the memory cells.

2. The semiconductor memory apparatus of claim 1, wherein the controller includes a bidirectional access control unit configured to provide the data transferred from the data input buffer to the memory cell array through the first local input and output lines in response to the test mode signal.

3. The semiconductor memory apparatus of claim 2, wherein the bidirectional access control unit is configured to provide the data transferred from the data input buffer to the memory cell array through second local input and output lines in response to the test mode signal.

4. The semiconductor memory apparatus of claim 3, wherein the switching unit is coupled to global input and output lines between the data input buffer and the write driver or between the data input buffer and the controller.

5. The semiconductor memory apparatus of claim 3, wherein the bidirectional access control unit is coupled to the first and second local input and output lines between the switching unit and the memory cell array.

6. The semiconductor memory apparatus of claim 1, wherein the memory cell performs reading/writing of data by a current driving scheme.

7. The semiconductor memory apparatus of claim 1, wherein the memory cell is a resistive memory cell.

8. A semiconductor memory apparatus, comprising:

a memory cell array configured to include a plurality of memory cells coupled between bit lines and source lines and driven by potential applied to word lines; and

a bidirectional access control unit configured to directly transfer data, provided in a data input buffer through data input and output pads, from the bit line to the source line of the memory cell in response to a test mode signal or directly transfer the data, applied to the data input buffer, from the source line to the bit line of the memory cell,

wherein the memory cell array and the bidirectional access control unit are configured to be directly coupled through a first local input and output lines which are substantially connected to bit lines of the memory cells.

9. The semiconductor memory apparatus of claim 8, further comprising a write driver configured to be driven by receiving data applied to the data input buffer and write the data in the memory cell array at a normal mode.

10. The semiconductor memory apparatus of claim 9, further comprising a switching unit configured to be coupled to the data input buffer and control a transfer path of the data applied to the data input buffer so that the data are transmitted to the bidirectional access control unit or the write driver in response to the test mode signal.

11. The semiconductor memory apparatus of claim 8, wherein the memory cell performs reading/writing of data by a current driving scheme.

12. The semiconductor memory apparatus of claim 8, wherein the memory cell is a resistive memory cell.

13. A test circuit for a semiconductor memory apparatus, comprising:

a switching unit configured to control a transfer path of data applied to a data input buffer through data input and output pads; and

a bidirectional access control unit configured to receive data applied to the data input buffer and directly transfer the data to a memory cell array in response to a test mode signal,

wherein the memory cell array and the bidirectional access control unit are configured to be directly coupled through a first local input and output lines or a second local input and output lines,

and the first local input and output lines are configured to substantially connected to bit lines of the memory cells, and the second local input and output lines are configured to substantially connected to source lines of the memory cells.

14. The test circuit of claim 13, wherein the bidirectional access control unit includes a path establishing unit configured to transmit the data, applied to the data input buffer, to the first local input and output lines or to the second local input and output lines in response to the test mode signal.

15. The test circuit of claim 14, wherein the path establishing unit transfers the data applied to the data input buffer to the first local input and output lines so as to write data of a first level in the memory cell array.

16. The test circuit of claim 14, wherein the path establishing unit transfers the data applied to the data input buffer to the second local input and output lines so as to write data of a second level in the memory cell array.

17. The test circuit of claim 14, wherein the path establishing unit includes:

a first path establishing unit including a first transfer device that is driven by a forward test mode signal generated from the test mode signal and transfers or blocks the data applied to the data input buffer to the first local input and output lines; and

a second transfer device configured to be driven by a reverse test mode signal generated from the test mode signal and couple the first local input and output lines and a ground terminal.

18. The test circuit of claim 14, wherein the path establishing unit includes:

a second path establishing unit including a third transfer device that is driven by a reverse test mode signal generated from the test mode signal and transfers or blocks the data applied to the data input buffer to the second local input and output lines; and

a fourth transfer device configured to be driven by a forward test mode signal generated from the test mode signal and couple the second local input and output lines and a ground terminal.