Radio frequency (RF) receiver with frequency planning and method therefor

• US 8,874,060 B2
• Filed: 12/18/2009
• Issued: 10/28/2014
• Est. Priority Date: 12/18/2009
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Wu, Sherry X., Koroglu, Mustafa H., Piovaccari, Alessandro, Poorfard, Ramin K.
• Primary Examiner(s): Nguyen, Simon
• Application Number:
  US12/641,540
• Publication Number:
  US 20110151816A1
• Time in Patent Office: 1,775 Days
• Field of Search: 455 75- 76, 455255-266, 4551641-1651, 455/181.1, 4551831-1832, 375/319, 375/372, 375338-339, 375/348
• US Class Current: 455/255
• CPC Class Codes: H04B 1/0007 wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage

Abstract

A radio frequency (RF) receiver with frequency planning includes an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal, and is controllable to adjust a frequency of the clock signal to a selected one of a predetermined number of frequencies within a predetermined frequency range in response to the clock control signal.

Claims

1. A radio frequency (RF) receiver with frequency planning comprising:

an analog receiver having an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal;

a digital processor having a first input for receiving said digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal;

a clock synthesizer having an input for receiving said clock control signal, and an output for providing said clock signal; and

wherein said digital processor controls said clock synthesizer to adjust a frequency of said clock signal to one of a predetermined number of frequencies within a predetermined frequency range in response to said clock control signal by selecting said frequency based on whether a spur, generated when said clock signal mixes with a signal generated in a magnetically coupled circuit, falls within a desired range.

2. The RF receiver of claim 1 wherein said digital processor comprises:

a digital signal processor (DSP) having a signal input for receiving said IF signal, a clock input for receiving said clock signal, and an output for providing said IF signal; and

a microcontroller (MCU) having a clock input for receiving said clock signal, a control input for receiving a channel selection input, and an output for providing said clock control signal.

3. The RF receiver of claim 1 wherein said an analog receiver, said digital processor, and said clock synthesizer are combined on a single integrated circuit.

4. The RF receiver of claim 1 wherein said clock synthesizer further has first and second terminals adapted to be coupled to a crystal.

5. The RF receiver of claim 1 wherein said digital IF signal is a low IF (LIF) signal.

6. The RF receiver of claim 1 wherein said digital IF signal is a zero IF (ZIF) signal.

7. The RF receiver of claim 1 wherein said clock synthesizer comprises a phase locked loop having an input for receiving said clock control signal, and an output for providing a PLL output signal at a frequency determined by said clock control signal, wherein said clock synthesizer provides said clock signal based on said PLL output signal.

8. The RF receiver of claim 7 wherein said clock synthesizer further comprises:

an oscillator having an output for providing a first clock signal;

a first divider having an input for receiving said first clock signal, and an output for providing a divided clock signal;

said phase locked loop further having a second input for receiving said divided clock signal; and

a second divider having an input for receiving said PLL output signal, and an output for providing said clock signal.

9. The RF receiver of claim 1 wherein said spur falls within said desired range when it does not overlap a frequency of a desired channel.

10. A radio frequency (RF) receiver with frequency planning comprising:

an analog receiver having an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal, and including a first magnetically coupled circuit associated with an aggressor circuit;

a clock synthesizer having an input for receiving a clock control signal, and an output for providing a clock signal to an input of said aggressor circuit that determines an operating frequency thereof; and

a controller having an output coupled to said clock synthesizer for providing said clock control signal thereto, said controller providing said clock control signal such that said operating frequency and all harmonics thereof fall outside a selected channel and based on whether a spur, generated when said clock signal mixes with a signal generated in said clock synthesizer, falls within a desired range.

11. The RF receiver of claim 10 wherein said aggressor circuit is said controller.

12. The RF receiver of claim 10 wherein said aggressor circuit is a digital signal processor.

13. The RF receiver of claim 10 wherein said controller is a microcontroller operable in response to stored program instructions.

14. The RF receiver of claim 10 wherein said first magnetically coupled circuit is a low noise amplifier (LNA).

15. The RF receiver of claim 10 wherein said clock synthesizer is controllable to adjust a frequency of said clock signal to a selected one of a predetermined number of frequencies within a predetermined frequency range in response to said clock control signal.

16. The RF receiver of claim 10 wherein said spur falls within said desired range when it does not overlap a frequency of a desired channel.

17. A radio frequency (RF) receiver with frequency planning comprising:

an aggressor circuit having an input for receiving a clock signal;

a receiver circuit having an input for receiving an RF input signal, and an output for providing an output signal;

a clock synthesizer having an input for receiving a clock control signal, and an output for providing said clock signal; and

a controller having an output coupled to said clock synthesizer for providing said clock control signal thereto, said controller performing dynamic frequency planning in response to a channel selection input to provide said clock signal at a selected frequency by taking into account whether a spur, generated when said clock signal mixes with a signal generated in a magnetically coupled circuit, falls within a desired range.

18. The RF receiver of claim 17 wherein said controller further performs dynamic frequency planning by taking into account whether said selected frequency and all harmonics thereof fall outside a selected channel.

19. The RF receiver of claim 17 wherein said magnetically coupled circuit comprises a low noise amplifier (LNA).

20. The RF receiver of claim 17 wherein said clock synthesizer comprises a crystal oscillator.

21. The RF receiver of claim 17 wherein said clock synthesizer comprises a voltage controlled oscillator.

22. The RF receiver of claim 17 wherein said spur falls within said desired range when it does not overlap a frequency of a desired channel.