Flash-DRAM hybrid memory module

• US 8,874,831 B2
• Filed: 07/26/2012
• Issued: 10/28/2014
• Est. Priority Date: 06/01/2007
• Status: Expired due to Fees

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Lee, Hyun, Chen, Chi-She, Solomon, Jeffrey C., Milton, Scott, Bhakta, Jayesh
• Primary Examiner(s): ELMORE, STEPHEN C
• Application Number:
  US13/559,476
• Publication Number:
  US 20130086309A1
• Time in Patent Office: 824 Days
• Field of Search: 711/103, 711/111, 711/112, 711/114, 711/154, 711/156, 365/185.33
• US Class Current: 711/103
• CPC Class Codes: G06F 1/185 Mounting of expansion boards
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.

Claims

1. A memory module couplable to a memory controller of a host system, comprising:

a non-volatile memory subsystem;

a data manager coupled to the non-volatile memory subsystem;

a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager; and

a controller operable to receive commands from the memory controller and to direct (i) operation of the non-volatile memory subsystem, (ii) operation of the volatile memory subsystem, and (iii) transfer of data between any two or more of the memory controller, the volatile memory subsystem, and the non-volatile memory subsystem based on at least one received command from the memory controller, wherein;

at least one of the volatile and non-volatile memory subsystems comprises one or more memory segments, each memory segment comprising at least one memory circuit, memory device, or memory die, and

the data manager is configured as a bi-directional data transfer fabric having two or more sets of data ports, a first set of data ports of the two or more sets of data ports is coupled to the volatile memory subsystem, a second set of data ports of the two or more sets of data ports is coupled to the non-volatile memory subsystem, the two or more sets of data ports being operable by the data manager to transfer data to or from one or more memory segments of the volatile or non-volatile memory subsystems, the data manager further including a data buffer for buffering data delivered to or from the non-volatile memory subsystem, and a data format module configured to format data to be transferred between any two or more of the memory controller, the volatile memory subsystem, and the non-volatile memory subsystem based on control information received from the controller.

2. The memory module of claim 1, wherein the data manager is operable to control one or more of data flow rate, data transfer size, data buffer size, data error monitoring, and data error correction in response to receiving at least one of a control signal and control information from the controller.

3. The memory module of claim 1, wherein the data manager controls data traffic between any two or more of the memory controller, the volatile memory subsystem, and the non-volatile memory subsystem based on instructions received from the controller.

4. The memory module of claim 3, wherein data traffic control relates to any one or more of data flow rate, data transfer size, data buffer size, data transfer bit width, formatting information, direction of data flow, and the starting time of data transfer.

5. The memory module of claim 1, wherein the controller configures at least one of a first memory address space of the volatile memory subsystem and a second memory address space of the non-volatile memory subsystem in response to at least one of a received command from the memory controller and memory address space initialization information of the memory module.

6. The memory module of claim 1, wherein the volatile memory subsystem comprises DRAM memory.

7. A method for managing a memory module by a memory controller, the memory module including volatile and non-volatile memory subsystems, the method comprising:

receiving control information from the memory controller, wherein the control information is received using a protocol of the volatile memory subsystem;

identifying a data path to be used for transferring data to or from the memory module using the received control information;

using a data manager and a controller of the memory module to transfer data between any two or more of the memory controller, the volatile memory subsystem, and the non-volatile memory subsystem based on at least one of the received control information and the identified data path;

operating the data manager as a bi-directional data transfer fabric with two or more sets of data ports, wherein a first set of data ports of the two or more sets of data ports is coupled to the volatile memory subsystems, and a second set of data ports of the two or more sets of data ports is coupled to the non-volatile memory subsystem;

operating the two or more sets of data ports to transfer data to or from one or more memory segments of the volatile or non-volatile memory subsystems based on control information received from the controller of the memory module; and

using the controller of the memory module to perform one or more of memory address translation, memory address mapping, address domain conversion, memory access control, data error correction, and data width modulation between any two or more of the memory controller, the volatile memory subsystem, and the non-volatile memory subsystem.

8. The method of claim 7, further comprising operating the data manager to control one or more of data flow rate, data transfer size, data width size, data buffer size, data error monitoring, data error correction, and the starting time of the transfer of data.

9. The memory module of claim 7, wherein at least one of the volatile and non-volatile memory subsystems comprises one or more memory segments.

10. The method of claim 7, further comprising directing transfer of data bi-directionally between the volatile and non-volatile memory subsystems using the data manager and in response to memory access commands received by the controller from the memory controller.

11. The method of claim 10, further comprising buffering the data transferred between the memory controller and non-volatile memory subsystem using the volatile memory subsystem.

12. The method of claim 7, further comprising using the controller to configure memory space in the memory module based on at least one of a command received from the memory controller, a programmable value written into a register, a value corresponding to a first portion of the volatile memory subsystem, a value corresponding to a first portion of the non-volatile memory subsystem, and a timing value.

13. The method of claim 12, wherein the controller configures the memory space of the memory module using at least a first portion of the volatile memory subsystem and a first portion of the non-volatile memory subsystem, and the controller presents a unified memory space to the memory controller.

14. The method of claim 12, wherein the controller configures the memory space in the memory module using partitioning instructions that are application-specific.

15. The method of claim 7, further comprising:

operating the volatile memory subsystem at a first clock frequency when the memory module is in a first mode of operation in which data is communicated between the volatile memory subsystem and the memory controller;

operating the non-volatile memory subsystem at a second clock frequency when the memory module is in a second mode of operation in which data is communicated between the volatile memory subsystem and the non-volatile memory subsystem; and

operating the volatile memory subsystem at a third clock frequency when the memory module is in the second mode of operation, the third clock frequency being less than the first clock frequency.