Memory cell presetting for improved memory performance

• US 8,874,846 B2
• Filed: 09/14/2012
• Issued: 10/28/2014
• Est. Priority Date: 06/01/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Franceschini, Michele M., Jagmohan, Ashish, Karidis, John P., Lastras-Montano, Luis A., Qureshi, Moinuddin K.
• Primary Examiner(s): Thai, Tuan
• Assistant Examiner(s): Waddy, Jr., Edward
• Application Number:
  US13/619,451
• Publication Number:
  US 20130013860A1
• Time in Patent Office: 774 Days
• Field of Search: 711/118, 711/103, 711/E12.008, 711/E12.001, 711/154, 714/773, 714/763
• US Class Current: 711/118
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means

Abstract

Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.

Claims

1. A method comprising:

using a computer system to identify a region in a phase change memory, the region comprising a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a first current state of the memory cells to a desired state of the memory cells and a second expected value when a write operation changes a specified state of the memory cells to the desired state of the memory cells, wherein the second expected value is closer than the first expected value to a desired value of the write performance characteristic;

setting the plurality of memory cells in the region to the specified state; and

writing data into the plurality of memory cells responsive to the setting,

wherein each of the memory cells consist of one of a SET state and a RESET state and wherein the desired state is selected to be either the RESET state or the SET state based on which state has a longer writer latency.

2. The method of claim 1, wherein the identifying is performed by software executing on the computer system.

3. The method of claim 1, wherein a value of the write performance characteristic of a memory cell in the region is not dependent on a current state of other memory cells in the region.

4. The method of claim 1, wherein the write performance characteristic is at least one of latency and energy utilized.

5. The method of claim 1, wherein the desired state is a low resistance value state.

6. The method of claim 1, wherein the data is checkpoint data.

7. The method of claim 1, wherein the memory is a persistent memory.

8. The method of claim 1, wherein the writing is further responsive to a system failure and the data comprises system state data.

9. A method comprising:

using a computer system to identify a region in a phase change memory, the region comprising a plurality of memory cells characterized by a write performance characteristic that is based on a difference between a current state of the memory cells and a desired state of the memory cells, wherein each of the memory cells consist of one of a SET state and a RESET state;

setting all of the plurality of memory cells in the region to a common specified state, wherein the common specified state is selected to be either the RESET state or the SET state based on which state has a longer write latency;

receiving a write request, the write request comprising write data and specifying a write address in the phase change memory that does not correspond to the region;

determining whether the write request should be redirected to the region in the phase change memory, the determining responsive to a state of the computer system and to whether an expected value of the write performance characteristic for writing to the phase change region in the phase change memory is closer to a desired value of the write performance characteristic than an expected value of the write performance characteristic for writing to the specified write address;

responsive to determining that the write request should not be redirected to the region in the phase change memory, writing the write data into the phase change memory at the specified write address in the phase change memory; and

responsive to determining that the write request should be redirected to the region in the phase change memory, writing the write data into the region in the phase change memory.

10. The method of claim 9, wherein the computer system is a memory controller.

11. The method of claim 9, wherein the identifying is performed by software executing on the computer system.

12. The method of claim 9, wherein upon determining that the write request should be redirected to the region in the phase change memory, a location within the region into which the write is redirected and the specified write address are stored in a line redirection table.

13. The method of claim 9, wherein the write performance characteristic is at least one of latency and energy utilized.

14. The method of claim 9, wherein upon determining that the write request should be redirected to the region in the phase change memory, a location within the region into which the write is redirected is stored at the specified write address in the phase change memory.

15. The method of claim 14, wherein the writing is performed with a fast write.

16. A system comprising:

a phase change memory comprising memory lines, each memory line comprising a plurality of memory cells, wherein each of the memory cells consist of one of a SET state and a RESET state;

a cache comprising cache lines corresponding to a subset of the memory lines; and

a memory controller in communication with the phase change memory and the cache, the memory controller configured to perform a method that comprises scheduling a request to set all of the plurality of memory cells of the subset of the memory lines to a common specified state in response to a cache line attaining a dirty state wherein the dirty state indicates that contents of the memory line are outdated, wherein the common specified state is selected to be either the RESET state or the SET state based on which state has a longer writer latency.

17. The system of claim 16, wherein the method further comprises:

receiving a read request at the memory controller;

determining whether the read request can be serviced faster by temporarily canceling a request to set the cells of a memory line to a specified state;

canceling the request to set the cells of the memory line to a common specified state responsive to determining that the read request can be serviced faster by temporarily canceling a request to set the cells of the memory line to a common specified state; and

reinitiating the request to set the cells of the memory line to the common specified state responsive to the canceling and to a completion of the read request.

18. The system of claim 16, wherein the scheduling a request comprises placing the request on a queue, wherein the request is not scheduled when the queue is full.

19. The system of claim 16, wherein the scheduling a request comprises placing the request on a queue, wherein the request is postponed when the queue is full.

20. The system of claim 16, wherein determining is responsive to a state of the request to set the cells of the memory line to the specified state.