Increasing security in inter-chip communication

• US 8,874,926 B1
• Filed: 03/01/2013
• Issued: 10/28/2014
• Est. Priority Date: 03/08/2012
• Status: Active Grant

• Current Assignee: National Technology & Engineering Solutions Of Sandia LLC (Honeywell International Inc.)
• Original Assignee: Sandia Corporation (Martin Marietta Corporation)
• Inventors: Edwards, Nathan J., Hamlet, Jason, Bauer, Todd, Helinski, Ryan
• Primary Examiner(s): PYZOCHA, MICHAEL J
• Application Number:
  US13/782,808
• Time in Patent Office: 606 Days
• Field of Search: 713/180, 726/23
• US Class Current: 713/180
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 21/556 involving covert channels, i.e. data leakage between processes inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H01L 23/57 Protection from inspection, reverse engineering or tampering
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/72 Signcrypting, i.e. digital signing and encrypting simultaneously
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/0869 involving random numbers or seeds
• CPC Class Codes: H04L 9/3247 involving digital signatures
• CPC Class Codes: H04L 9/3278 using physically unclonable functions [PUF]

Abstract

An apparatus for increasing security in inter-chip communication includes a sending control module, a communication bus, and a receiving control module. The communication bus is coupled between the sending control module and the receiving control module. The sending control module operates to send data on the communication bus, disable the communication bus when threats are detected, or both.

Claims

1. An apparatus to increase security on a bus comprising:

a communication bus;

a sending controller coupled to the communication bus to send data across the communication bus;

a switch coupled to the communication bus and further coupled to be enabled and disabled by the sending controller; and

an intrusion prevention circuit configured to prevent communication on the communication bus by altering at least a first analog characteristic of the communication bus, when the switch is enabled by the sending controller, wherein the intrusion prevention circuit is configured to be decoupled from the communication bus, when the switch is disabled by the sending controller.

2. The apparatus of claim 1, wherein the sending controller includes a bus sensing module coupled to perform a bus integrity check on the communication bus, wherein the bus integrity check senses at least a second analog characteristic of the communication bus, and wherein the sending controller is configured to initiate the bus integrity check when the switch is disabled by the sending controller.

3. The apparatus of claim 1, wherein the first analog characteristic and the second analog characteristic is a same electrical characteristic, and wherein the electrical characteristic is a bus capacitance of the communication bus.

4. The apparatus of claim 1, wherein the sending controller includes a system sense module coupled to perform a system integrity check on at least a portion of an embedded system that includes the sending controller and the communication bus, wherein the system integrity check includes measuring analog characteristics of the embedded system.

5. The apparatus of claim 4, wherein performing the system integrity check includes sending challenges signals and receiving system responses from sending the challenge signals.

6. The apparatus of claim 1 further comprising a receiving controller coupled to the communication bus to receive the data sent by the sending controller.

7. A method of increasing security on a communication bus, the method comprising:

de-coupling an intrusion prevention circuit from the communication bus to enable communication across the communication bus;

performing a bus integrity check of the communication bus while the intrusion prevention circuit is de-coupled, wherein the bus integrity check includes measuring at least a first analog characteristic of the communication bus;

sending a first communication across the communication bus, if the bus integrity check is passed; and

coupling the intrusion prevention circuit to the communication bus after sending the first communication, the intrusion prevention circuit coupled to alter at least a second analog characteristic of the communication bus to disable the communication across the communication bus.

8. The method of claim 7 further comprising:

performing a system integrity check of at least a portion of an embedded system, the embedded system including the intrusion prevention circuit and the communication bus, wherein performing the system integrity check includes measuring system analog characteristics.

9. The method of claim 8, wherein performing the system integrity check includes sending challenge signals and receiving system responses from sending the challenge signals.

10. The method of claim 7, wherein the first analog characteristic and the second analog characteristic is a same electrical characteristic, and wherein the electrical characteristic is a bus resistance of the communication bus.