Memory management in a non-volatile solid state memory device

• US 8,874,993 B2
• Filed: 01/02/2013
• Issued: 10/28/2014
• Est. Priority Date: 07/23/2009
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Eleftheriou, Evangelos S, Iliadis, Ilias, Haas, Robert, Hu, Xiaoyu
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US13/732,830
• Publication Number:
  US 20130191704A1
• Time in Patent Office: 664 Days
• Field of Search: 714/763, 714/42
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A non-volatile solid state memory device and method for balancing write/erase cycles among blocks to level block usage. The non-volatile solid state memory device includes a memory unit having data stored therein and a controller with logic for programming the memory unit according to a monitored occurrence of an error during a read operation. The method includes monitoring an occurrence of an error during a read operation in a memory unit of the device and programming the memory unit according to the monitored occurrence of the error.

Claims

1. A non-volatile solid state memory device comprising:

a memory unit having (i) stored data which is readable using a read operation; and

(ii) an error-correcting code for correcting a potential error in said data;

a controller with a logic for programming said memory unit according to a monitored occurrence of said error during said read operation, by monitoring end of life blocks stored in the memory unit;

a first counter coupled to the controller and associated with a first block in the memory unit, the first counter being configured to count the accumulated number of errors since a second counter was last incremented, wherein the first counter is reset at the being nine of each of a plurality of write-erase cycles of the memory unit; and

the second counter coupled to the first counter and configured to count the number of times a threshold is exceeded within the write-erase cycles by counting the number of times the first counter exceeds the threshold, wherein a predetermined count by the second counter indicates that an end of life of the first block has been reached.

2. The device according to claim 1, wherein said read operation comprises monitoring the rate of errors.

3. The device according to claim 1, wherein said memory unit is subdivided into die, each comprising at least one block, wherein said read operation is carried out for each block in each die by maintaining a per-block counter of said occurrence of said error.

4. The device according to claim 1, wherein said read operation comprises monitoring an error in a window of a maximum consecutive read operations.

5. The device according to claim 1, wherein:

said memory unit maintains a per-block counter of write-erase data; and

said controller logic is carried out in response to both error monitored and write-erase data maintained.

6. The device according to claim 1, wherein said memory unit is subdivided into dice, each die comprising at least one block.

7. The device according to claim 6, wherein said memory is configured to set apart a block of said memory unit, and implement wear-leveling for a block that is distinct from said block that has been set apart.

8. The device according to claim 7, wherein said setting apart a block is performed independent of the number of said errors monitored or the number of write-erase operations performed in each block of said memory unit.

9. The device according to claim 7, wherein said setting apart a block is decided or refined based on the number of errors monitored or write-erase data maintained.

10. The device according to claim 6, wherein:

said memory unit sets apart a block of said memory unit; and

said controller logic comprises releasing and using said block that has been set apart, wherein releasing and using said block that has been set apart is performed if said monitored occurrence of an error or rate of errors exceeds a threshold indicative of a depletion of writable memory space in said memory unit.

11. The device according to claim 10, wherein said controller logic initiates a migration of data towards another memory device, wherein initiating a migration of data towards another memory device is performed if said monitored occurrence or said rate of errors exceeds a threshold indicative of a depletion of writable memory space in said memory unit.

12. A computer system for managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage, said system comprising:

a non-volatile solid state memory device with a memory unit having stored therein data that is readable by a read operation and is correctable using error-correcting code; and

a non-transitory article of manufacture tangibly embodying computer readable instructions which, when implemented, cause said computer system to carry out the steps of a method of managing said memory unit of said non-volatile solid state memory device, wherein said method comprises the steps of;

monitoring an occurrence of an error during said read operation in said memory unit of said device;

monitoring a first counter coupled to the controller and associated with a first block in the memory unit, the first counter being configured to count the accumulated number of errors since a second counter was last incremented, wherein the first counter is reset at the being nine of each of a plurality of write-erase cycles of the memory unit;

monitoring the second counter coupled to the first counter and configured to count the number of times a threshold is exceeded within the write-erase cycles by counting the number of times the first counter exceeds the threshold, wherein a predetermined count by the second counter indicates that an end of life of the first block has been reached;

marking the first block as bad in response to the predetermined count having been reached by the second counter; and

programming said memory unit according to said monitored occurrence of said error;

wherein the step of monitoring the occurrence of said error is carried out for at least one said block; and

wherein said step of programming comprises wear-leveling said monitored block according said error monitored for said monitored block.

13. The computer system according to claim 12, wherein said step of monitoring the occurrence of an error comprises monitoring the rate of errors.

14. The computer system according to claim 12, wherein said memory unit is subdivided into dies, each die comprising at least one block, wherein said step of monitoring the occurrence of an error is carried out for each block of each die by maintaining a per-block counter of the occurrence of said error.

15. The computer system according to claim 12, wherein said step of monitoring the occurrence of an error comprises:

monitoring an error in a window of a maximum consecutive read operations.

16. The computer system according to claim 12, further comprising:

maintaining a per-block counter of write-erase data, and

wherein said step of programming said memory is carried out according to both said error monitored and said write-erase data maintained.

17. The computer system according to claim 12, wherein said memory unit is subdivided into dies, each die comprising at least one block.

18. The computer system according to claim 17, where the method further comprises:

setting apart a writable block of said memory unit, wherein wear-leveling is implemented for a block that is distinct from said block that has been set apart.

19. The computer system according to claim 18, wherein setting apart a writable block is performed independent of the number of said errors monitored or the number of write-erase operations performed in each block of said memory unit.

20. The computer system according to claim 18, wherein setting apart a writable block is decided or refined based on the number of errors monitored or write-erase data maintained.

21. The computer system according to claim 17, wherein the method further comprises:

setting apart a writable block of said memory unit; and

releasing said block that has been set apart if said monitored occurrence of an error or rate of errors exceeds a threshold indicative of a depletion of writable memory space in said memory unit.

22. The computer system according to claim 21, wherein the method further comprises:

initiating a migration of data towards another memory device if said monitored occurrence or said rate of errors exceeds a threshold indicative of a depletion of writable memory space in said memory unit.