Methods of fabricating wafer-level flip chip device packages

• US 8,877,561 B2
• Filed: 03/04/2013
• Issued: 11/04/2014
• Est. Priority Date: 06/07/2012
• Status: Active Grant

• Current Assignee: Cooledge Lighting Inc.
• Original Assignee: Cooledge Lighting Inc.
• Inventors: Tischler, Michael A.
• Primary Examiner(s): Patel, Reema
• Application Number:
  US13/784,417
• Publication Number:
  US 20130330853A1
• Time in Patent Office: 610 Days
• Field of Search: 438/118, 438/119
• US Class Current: 438/119
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05638 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/0568 Molybdenum [Mo] as principal constituent
• CPC Class Codes: H01L 2224/05686 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/06102 the bonding areas being at different heights
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/27003 for holding or transferring the layer preform
• CPC Class Codes: H01L 2224/27436 : Lamination of a preform, e.g. foil, sheet or layer
• CPC Class Codes: H01L 2224/29082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/2929 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29298 : Fillers
• CPC Class Codes: H01L 2224/32227 : the layer connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73104 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/83385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2933/0033 : relating to semiconductor body packages
• CPC Class Codes: H01L 2933/0041 : relating to wavelength conversion elements
• CPC Class Codes: H01L 2933/0066 : relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0095 : Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/50 : Wavelength conversion elements
• CPC Class Codes: H01L 33/505 : characterised by the shape, e.g. plate or foil
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon.

Claims

1. A method of fabricating an electronic device, the method comprising:

applying an anisotropic conductive adhesive (ACA) onto a surface of a wafer comprising a plurality of unsingulated chips, each chip comprising a plurality of electrical contacts each having a top surface substantially coplanar with or recessed below a surface of the chip surrounding the electrical contact;

thereafter, singulating the wafer into individual chips, each chip comprising first and second electrical contacts with the ACA thereover;

providing a substrate having first and second conductive traces on a first surface thereof in a bonding region, the first and second conductive traces being separated by a gap therebetween;

positioning the first and second electrical contacts of one of the chips over the first and second conductive traces, a portion of the ACA being disposed between the electrical contacts and the traces; and

bonding the first and second electrical contacts of the chip to the first and second traces, respectively, thereby establishing electrical connection between at least one of (i) the first electrical contact and the first trace or (ii) the second electrical contact and the second trace, but without electrically bridging the traces together or electrically bridging the electrical contacts together,

wherein, for each unsingulated chip, each of the plurality of electrical contacts is in direct physical contact with (i) a semiconductor portion of the wafer thereunder and (ii) the ACA.

2. The method of claim 1, wherein the substrate is a yielding substrate.

3. The method of claim 1, wherein bonding comprises applying pressure to at least one of the substrate or the chip.

4. The method of claim 3, wherein applying pressure to at least one of the substrate or the chip comprises compressing the substrate and the chip between a substantially rigid surface and a substantially compliant surface to adhere the first and second electrical contacts to the first and second traces.

5. The method of claim 3, wherein:

the first and second electrical contacts are non-coplanar, and

applying pressure to at least one of the substrate or the chip comprises compressing the substrate and the chip between a substantially rigid surface and a substantially compliant surface to adhere the first and second electrical contacts to the first and second traces notwithstanding the non-coplanarity between the first and second electrical contacts.

6. The method of claim 1, wherein bonding comprises applying heat to at least one of the substrate or the chip.

7. The method of claim 1, wherein bonding comprises applying heat and pressure to at least one of the substrate or the chip.

8. The method of claim 1, wherein bonding comprises applying a magnetic field and heat to at least one of the substrate or the chip.

9. The method of claim 1, wherein the substrate is flexible but not deformable.

10. The method of claim 1, wherein the substrate is deformable but not flexible.

11. The method of claim 1, wherein the substrate is flexible and deformable.

12. The method of claim 1, wherein the first and second electrical contacts are non-coplanar.

13. The method of claim 1, wherein providing the substrate comprises printing the first and second traces thereon.

14. The method of claim 1, wherein providing the substrate comprises forming the first and second traces thereon by at least one of evaporation, physical vapor deposition, chemical vapor deposition, sputtering, lamination, or plating.

15. The method of claim 1, wherein the ACA comprises an anisotropic conductive film.

16. The method of claim 15, wherein applying the ACA over the wafer comprises laminating the anisotropic conductive film to the wafer.

17. The method of claim 1, wherein singulating the wafer comprises cutting, sawing, dicing, laser cutting, water jet cutting, or die cutting.

18. The method of claim 1, wherein the positioned chip comprises a light-emitting diode (LED) die.

19. The method of claim 18, wherein the LED die comprises an inorganic LED die.

20. The method of claim 19, wherein at least a portion of the LED die comprises a semiconductor material comprising at least one of silicon, GaAs, InAs, AlAs, InP, GaP, AlP, InSb, GaSb, AlSb, GaN, InN, AlN, SiC, ZnO, or an alloy or mixture thereof.

21. The method of claim 1, wherein the positioned chip comprises a laser.

22. The method of claim 1, wherein providing the substrate and bonding the electrical contacts to the traces are performed in a roll-to-roll process.

23. The method of claim 1, wherein the first and second electrical contacts are substantially coplanar and, at least in the bonding region, a height of the first and second traces above the first surface of the substrate does not exceed 10 μ

m.

24. The method of claim 1, further comprising, substantially simultaneously with the bonding of the electrical contacts to the traces, bonding electrical contacts of at least one additional chip to additional traces on the substrate.

25. The method of claim 1, further comprising forming a phosphor material over at least a portion of the chip, the phosphor material converting at least a portion of light emitted by the chip to light of a different wavelength.

26. The method of claim 1, wherein the ACA is at least partially transparent.

27. The method of claim 1, wherein, for each unsingulated chip, the top surface of each of the plurality of electrical contacts is absolutely coplanar with or recessed below the surface of the chip surrounding the electrical contact.

28. The method of claim 1, wherein, for each unsingulated chip, the top surface of each of the plurality of electrical contacts is recessed below the surface of the chip surrounding the electrical contact by more than 3 μ

m.

29. The method of claim 1, wherein the substrate is flexible.

30. The method of claim 1, wherein, for each unsingulated chip, the top surface of at least one of the plurality of electrical contacts extends above the surface of the chip surrounding the electrical contact by 3 μ

m or less.

31. The method of claim 1, wherein, for each unsingulated chip, each of the plurality of electrical contacts comprises a metal silicide or metal nitride compound.

32. The method of claim 1, wherein, for each unsingulated chip, each of the plurality of electrical contacts comprises a metal layer and a second layer comprising a metal silicide or metal nitride compound.

33. The method of claim 1, wherein, for each unsingulated chip, each of the plurality of electrical contacts comprises at least one of Al, Cr, Ti, Au, Ni, Ag, or Mo.