Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method

• US 8,877,565 B2
• Filed: 06/28/2007
• Issued: 11/04/2014
• Est. Priority Date: 06/28/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Li, Yonggang, Salama, Islam, Gurumurthy, Charan
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US11/769,852
• Publication Number:
  US 20090001550A1
• Time in Patent Office: 2,686 Days
• Field of Search: 438/928, 438/940, 438/690, 438/584, 257/E23.003, 257/E23.007, 257/E23.586, 257/E23.596, 257/E23.578, 257/E23.577, 361/751, 361/779, 427/437, 205/126
• US Class Current: 438/125
• CPC Class Codes: H05K 2201/0394 Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
• CPC Class Codes: H05K 2201/09563 Metal filled via plated through-hole filled with insulating material H05K2201/0959
• CPC Class Codes: H05K 3/0035 of blind holes, i.e. having a metal layer at the bottom
• CPC Class Codes: H05K 3/422 characterised by electroless plating method; pretreatment therefor
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4652 Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof.

Claims

1. A method of fabricating a substrate core structure comprising:

providing a starting insulating layer;

forming an initial conductive layer on said starting insulating layer;

laser drilling a first set of via openings through the starting insulating layer without laser drilling through said conductive layer such that said first set of via openings extend to said first conductive layer;

filling the first set of via openings with a conductive material to provide a first set of conductive vias;

after filling the first set of via openings, providing a first patterned conductive layer on one side of the starting insulating layer, and a second patterned conductive layer on another side of the starting insulating layer, the first set of conductive vias contacting the first patterned conductive layer at one side thereof, and the second patterned conductive layer at another side thereof;

providing a first supplemental insulating layer onto the first patterned conductive layer and a second supplemental insulating layer on the second patterned conductive layer;

laser drilling a second set of via openings through the first supplemental insulating layer, the via openings of the second set extending to the first patterned conductive layer and laser drilling a third set of via openings through the second supplemental insulating layer, the third set of via openings extending to the second patterned conductive layer;

filling the second set of via openings with a conductive material to provide a second set of conductive vias and filling the third set of via openings with a conductive material to form a third set of conductive vias;

providing a first supplemental patterned conductive layer onto an exposed side of the first supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer at one side thereof and the first supplemental patterned conductive layer at another side thereof; and

providing a second supplemental patterned conductive layer on the exposed side of the second supplemental insulating layer, the third set of conductive vias contacting the second patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.

2. The method of claim 1, wherein providing the first supplemental insulating layer includes laminating the supplemental insulating layer.

3. The method of claim 1, wherein the first set of conductive vias, the first patterned conductive layer, the second patterned conductive layer, the second set of conductive vias and the first supplemental patterned conductive layer each comprise at least one of copper, nickel and silver.

4. The method of claim 1, wherein the starting insulating layer and the supplemental insulating layer each comprise at least one of a glass epoxy resin and bismaleimide-triazine (BT).

5. The method of claim 1, further comprising subjecting a combination of the starting insulating layer, the first set of conductive vias, the first patterned conductive layer, the second patterned conductive layer, the first supplemental insulating layer, the second supplemental insulating layer, the second set of conductive vias, the third set of conductive vias, the first supplemental patterned conductive layer and the second supplemental patterned conductive layer to hot pressing to bond the conductive vias to pad sections of the patterned conductive layers. patterned conductive layer each comprise at least one of copper, nickel and silver.

6. The method of claim 1, wherein filling the first set of via openings and filling the second set of via openings includes using fast electroless plating.

7. The method of claim 6, wherein fast electroless plating includes fast electroless copper plating.

8. The method of claim 1, wherein:

providing the first patterned conductive layer includes patterning the conductive layer by way of etching; and

providing the second patterned conductive layer includes;

providing a second conductive layer onto said another side of the starting insulating layer; and

patterning the second conductive layer by way of etching.

9. The method of claim 8, wherein providing a second conductive layer comprises laminating the second conductive layer.

10. The method of claim 1, wherein:

providing the first patterned conductive layer includes;

removing, by way of etching, the initial conductive layer after filling the first set of via openings by way of etching;

providing the first patterned conductive layer by using a semi-additive process; and

providing the second patterned conductive layer by using a semi-additive process.

11. The method of claim 10, wherein the initial conductive layer has a thickness between about 1 and about 2 microns.

12. The method of claim 10, wherein removing the initial conductive layer comprises q-etching the initial conductive layer.

13. The method of claim 10, wherein filling the first set of via openings and filling the second set of via openings includes using selective fast electroless copper plating.