Method of manufacturing thin film transistor with oxide semiconductor using sputtering method

• US 8,877,569 B2
• Filed: 04/25/2012
• Issued: 11/04/2014
• Est. Priority Date: 02/06/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Oikawa, Yoshiaki, Maruyama, Hotaka, Godo, Hiromichi, Kawae, Daisuke, Yamazaki, Shunpei
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US13/455,425
• Publication Number:
  US 20120214276A1
• Time in Patent Office: 923 Days
• Field of Search: 438/104, 438/149, 438/478, 438/479, 438/493, 438/584, 438/585, 438/590, 438/591, 438/608, 438/FOR.184, 438/FOR.201, 257/E21.462, 257/E29.273, 204/192.14, 204/192.15, 204/192.17, 204/192.23, 204/192.25
• US Class Current: 438/149
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiO_X is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiO_X and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiO_X. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiO_X.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a gate electrode layer over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming a first oxide semiconductor layer including In and SiO_x over the gate insulating layer by a sputtering method using a first oxide semiconductor target including SiO₂ at 5 wt % or higher and 50 wt % or lower; and

forming a source region, a drain region, and a pixel electrode over the first oxide semiconductor layer by a sputtering method using a second oxide semiconductor target including In, Si and O,

wherein the source region, the drain region, and the pixel electrode are formed from a second oxide semiconductor layer including In and O.

2. A method of manufacturing a semiconductor device according to claim 1, wherein a channel region is formed in the first oxide semiconductor layer.

13. A method of manufacturing a semiconductor device according to claim 1, wherein the first oxide semiconductor target further includes Sn.

14. A method of manufacturing a semiconductor device according to claim 1, wherein the-second oxide semiconductor target further includes Sn.

3. A method of manufacturing a semiconductor device, comprising:

forming a gate electrode layer over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming a first oxide semiconductor layer including In over the gate insulating layer by a sputtering method using a first target including In and O; and

forming a source region, a drain region, and a pixel electrode over the first oxide semiconductor layer by a sputtering method using a second target including In and O,

wherein the source region, the drain region, and the pixel electrode are formed from a second oxide semiconductor layer including In, N, and O.

4. The method of manufacturing a semiconductor device according to claim 3, wherein a channel region is formed in the first oxide semiconductor layer.

5. The method of manufacturing a semiconductor device according to claim 3, the first oxide semiconductor layer further including Sn.

6. The method of manufacturing a semiconductor device according to claim 3, the first oxide semiconductor layer further including Si.

7. The method of manufacturing a semiconductor device according to claim 3, the second oxide semiconductor layer further including Sn.

8. A method of manufacturing a semiconductor device, comprising:

forming a gate electrode layer over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming a first oxide semiconductor layer including In and Si over the gate insulating layer by a sputtering method using a first target including In, Si, and O where a concentration of SiO₂ is 5 wt % or higher and 50 wt % or lower; and

forming a source region, a drain region, and a pixel electrode over the first oxide semiconductor layer by a sputtering method using a second target including In and O,

wherein the source region, the drain region, and the pixel electrode are formed from a second oxide semiconductor layer including In and O.

9. The method of manufacturing a semiconductor device according to claim 8, wherein a channel region is formed in the first oxide semiconductor layer.

10. The method of manufacturing a semiconductor device according to claim 8, the first oxide semiconductor layer further including Sn.

11. The method of manufacturing a semiconductor device according to claim 8, the first oxide semiconductor layer further including Si.

12. The method of manufacturing a semiconductor device according to claim 8, the second oxide semiconductor layer further including Sn.