Methods of forming field effect transistors on substrates

• US 8,877,589 B2
• Filed: 04/17/2013
• Issued: 11/04/2014
• Est. Priority Date: 08/30/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hanson, Robert J., Tang, Sanh D.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US13/865,117
• Publication Number:
  US 20130230957A1
• Time in Patent Office: 566 Days
• Field of Search: 438/268, 438/270, 438/197, 438/199, 438/589, 257/E21.428
• US Class Current: 438/268
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.

Claims

1. A method of forming a field effect transistor on a substrate, the field effect transistor comprising a pair of source/drain regions, a channel region received intermediate and elevationally below the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:

providing a pair of trench isolation regions extending into a background doped semiconductive material over a substrate;

ion implanting conductivity enhancing impurity dopant into the background doped semiconductive material between the pair of trench isolation regions to form highest dopant concentration portions of the pair of source/drain regions, the highest dopant concentration portions comprising 1×

10¹³ to 1×

10¹⁶ ions/cm³;

conducting a dopant activation anneal, the semiconductive material having an exposed uppermost surface during the implanting and the anneal;

prior to conducting the dopant activation anneal, ion implanting conductivity modifying impurity dopant into semiconductive material of the substrate to form at least one lower dopant concentration portion proximate each highest dopant concentration portion, the conductivity modifying impurity dopant being of an opposite conductivity type than dopant in the highest conductivity concentration portions;

after the dopant activation anneal, etching an opening through the highest dopant concentration portion and lower dopant portion and into the background doped semiconductive material, the opening extending to a first depth that is less than a second depth to which the isolation regions extend; and

depositing material from which a conductive portion of the transistor gate is made into the opening.

2. The method of claim 1 wherein the deposited material from which a conductive portion of the transistor gate is made comprises elemental-form metal.

3. The method of claim 1 wherein the deposited material from which a conductive portion of the transistor gate is made comprises a conductive metal compound.

4. The method of claim 1 wherein the deposited material from which a conductive portion of the transistor gate is made comprises conductively doped semiconductive material.

5. The method of claim 1 wherein the pair of source/drain regions is formed within bulk monocrystalline background doped semiconductive material of the substrate.

6. The method of claim 5 wherein the field effect transistor gate is formed outwardly of the bulk monocrystalline semiconductive material.

7. The method of claim 1 wherein the pair of source/drain regions comprises elevated source/drain regions of a horizontally oriented field effect transistor.

8. The method of claim 6 wherein the substrate comprises bulk monocrystalline semiconductive material, the elevated source/drain regions being formed on the bulk monocrystalline semiconductive material.

9. A method of forming a field effect transistor on a substrate, the field effect transistor comprising a pair of laterally spaced conductively doped source/drain regions, a channel region received intermediate and elevationally below the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:

providing a pair of trench isolation regions within a semiconductive material of a substrate;

ion implanting into an implant region of the semiconductive material of the substrate between the pair of trench isolation regions to a highest dopant concentration for the pair of source/drain;

after the ion implanting, conducting a dopant activation anneal of the implant region, an uppermost surface of the semiconductive material being exposed during the implanting and the anneal;

prior to conducting the dopant activation anneal, ion implanting conductivity modifying impurity dopant into semiconductive material of the substrate to form at least one lower dopant concentration portion below the implant region, the opening being etched through the portion, the conductivity modifying impurity dopant being of an opposite conductivity type relative to the source/drain region dopant;

after the dopant activation anneal, etching an opening through the implant region and through the lower dopant concentration portion into material of the substrate, the opening extending less than a depth of the trench isolation regions into the semiconductive material; and

forming conductive material of the transistor gate within the opening.

10. The method of claim 9 wherein the opening is laterally centered relative to the implant region in at least one straight line cross section of the substrate.