Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom

• US 8,877,619 B1
• Filed: 01/23/2013
• Issued: 11/04/2014
• Est. Priority Date: 01/23/2012
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Thompson, Scott E., Shifren, Lucian, Ranade, Pushkar, Scudder, Lance, Zhao, Dalong, Pradhan, Sameer, Bakhisher, Teymur
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Perkins, Pamela E
• Application Number:
  US13/748,418
• Time in Patent Office: 650 Days
• Field of Search: 438/217, 438/227
• US Class Current: 438/527
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Abstract

Structures and processes are provided that can be used for effectively integrating different transistor designs across a process platform. In particular, a bifurcated process is provided in which dopants and other processes for forming some transistor types may be performed prior to STI or other device isolation processes, and other devices may be formed thereafter. Thus, doping and other steps and their sequence with respect to the STI process can be selected to be STI-first or STI-last, depending on the device type to be manufactured, the range of device types that are manufactured on the same wafer or die, or the range of device types that are planned to be manufactured using the same or similar mask sets.

Claims

1. A method of manufacture of an integrated circuit, comprising the steps of:

providing a substrate;

fabricating at least a portion of first integrated structures in at least one first area of the substrate using a first process that includes forming at least one of a trench capacitor, at least a part of a flash memory cell structure, or a first shallow trench isolation structure;

fabricating at least a portion of second integrated structures in at least one second area of the substrate, the fabricating of the portion of the second integrated structures comprising defining at least a first targeted dopant profile in the at least one second area and forming an epitaxial layer on the at least one second area, the first target dopant profile comprising a first section with a first doping concentration at a surface of the at least one second area defining a heavily doped screening layer and a second section below the first section with a second doping concentration less than the first doping concentration defining a well layer, wherein the fabrication of the portion of the second integrated structures includes using a second process that is at a reduced thermal budget compared with the first process; and

completing the first and second integrated structures to form the integrated circuit.

2. The method of claim 1, wherein the step of fabricating the portion of second integrated structures further comprises forming isolation structures in the epitaxial layer.

3. The method of claim 2, wherein the step of fabricating the portion of second integrated structures further includes the step of etching the at least one second area of the substrate to a preselected depth prior to forming the epitaxial layer.

4. The method of claim 1, wherein the step of fabricating the portion of second integrated structures includes forming doped regions using ion implantation in a process selected to result in the first target dopant profile.

5. The method of claim 4, wherein the step of fabricating a portion of second integrated structures includes etching the at least one second area of the substrate to a preselected depth prior to the forming of the doped regions, and forming an epitaxial layer after the forming of the doped regions.