Damascene process for aligning and bonding through-silicon-via based 3D integrated circuit stacks
First Claim
1. A method comprising:
- providing a first wafer having first and second surfaces, a first device layer, and at least one first through-silicon-via (TSV) filled with a conductive material;
providing a second wafer having first and second surfaces and a second device layer on the first surface of the second wafer;
forming at least one second TSV in the first surface of the second wafer;
filling each second TSV in the second wafer with an alignment material;
thinning the second surface of the second wafer;
aligning the first and second wafers;
bonding the first and second wafers;
removing the alignment material from the second wafer; and
filling each second TSV in the second wafer with a conductive material.
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Accused Products
Abstract
Through-silicon-via (TSV) based 3D integrated circuit (3D IC) stacks are aligned, bonded and electrically interconnected using a transparent alignment material in the TSVs until the wafers are bonded. Embodiments include providing a first wafer having a first device layer and at least one first TSV filled with a conductive material, providing a second wafer having a second device layer, forming at least one second TSV in the second wafer, filling each second TSV with an alignment material, thinning the second wafer until the transparent material extends all the way through the wafer, aligning the first and second wafers, bonding the first and second wafers, removing the alignment material from the second wafer, and filling each second TSV in the second wafer with a conductive material.
8 Citations
19 Claims
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1. A method comprising:
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providing a first wafer having first and second surfaces, a first device layer, and at least one first through-silicon-via (TSV) filled with a conductive material; providing a second wafer having first and second surfaces and a second device layer on the first surface of the second wafer; forming at least one second TSV in the first surface of the second wafer; filling each second TSV in the second wafer with an alignment material; thinning the second surface of the second wafer; aligning the first and second wafers; bonding the first and second wafers; removing the alignment material from the second wafer; and filling each second TSV in the second wafer with a conductive material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method comprising:
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providing a first wafer having first and second surfaces, a first device layer, and at least one first through-silicon-via (TSV) filled with a conductive material; providing a second wafer having first and second surfaces, a second device layer, and at least one second TSV corresponding to the at least one first TSV of the first wafer, the at least one second TSV having no electrically conductive material; aligning each first TSV in the first wafer with the corresponding second TSV in the second wafer; bonding the first and second wafers; and electrically interconnecting the first and second wafers through the at least one first and the at least one second TSVs. - View Dependent Claims (15, 16, 17, 18)
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19. A method comprising:
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providing a first wafer having first and second surfaces, a first device layer, and at least two through-silicon-vias (TSVs) filled with copper; providing at least two second wafers, each having first and second surfaces and a second device layer on the first surface of the at least two second wafers; etching at least two second TSVs in the first surface of each second wafers; filling each second TSV in each second wafer with an alignment material which is transparent to at least one of infrared, visible, and ultraviolet (UV) light; thinning the second surface of each second wafer until the alignment material extends all the way through the wafer; aligning the first TSVs in the first wafer with the second TSVs in one second wafer; bonding the first wafer and the one second wafer with an adhesive bonding material; etching the alignment and bonding materials through the second TSVs of the one second wafer, to expose the filled first TSVs of the first wafer; filling the second TSVs in the one second wafer with copper; and repeating for each additional second wafer the steps comprising; aligning the second TSVs in the bonded second wafer with the second TSVs in an additional second wafer; bonding further the bonded second wafer with the additional second wafer; etching the alignment and bonding material in the second TSVs of the additional second wafer thereby exposing the filled second TSVs of the bonded second wafer; and filling the second TSVs of the additional second wafer with copper.
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Specification