Methods of forming printable integrated circuit devices by selective etching to suspend the devices from a handling substrate and devices formed thereby

• US 8,877,648 B2
• Filed: 03/26/2010
• Issued: 11/04/2014
• Est. Priority Date: 03/26/2009
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: Semprius, Inc.
• Inventors: Bower, Christopher, Menard, Etienne, Meitl, Matthew
• Primary Examiner(s): HENRY, CALEB E
• Application Number:
  US12/732,868
• Publication Number:
  US 20100248484A1
• Time in Patent Office: 1,684 Days
• Field of Search: 438/700, 438/118, 438/458
• US Class Current: 438/700
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate

Abstract

Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.

Claims

1. A method of forming an integrated circuit device, comprising:

forming a substrate comprising a semiconductor active layer on an underlying sacrificial layer;

forming a multi-layer electrical interconnect network comprising a plurality of interlayer dielectric layers, on the substrate;

selectively etching through the plurality of interlayer dielectric layers to expose an upper surface of the semiconductor active layer;

encapsulating the multi-layer electrical interconnect network with an inorganic capping layer that contacts the exposed upper surface of the semiconductor active layer;

selectively etching through the inorganic capping layer and the semiconductor active layer to expose the sacrificial layer; and

then

removing the sacrificial layer from the substrate to thereby suspend the semiconductor active layer from the substrate,

wherein said encapsulating is preceded by roughening an upper surface of the semiconductor active layer.

2. The method of claim 1, wherein said roughening the upper surface of the semiconductor active layer comprises exposing the upper surface of the semiconductor active layer to a plasma etchant.

3. The method of claim 1, wherein said removing the sacrificial layer comprises exposing the sacrificial layer to an etchant using the inorganic capping layer as an etching mask to protect the multi-layer electrical interconnect network from etching damage.

4. A method of forming an integrated circuit device, comprising:

forming a substrate comprising a semiconductor active layer on an underlying sacrificial layer;

forming a multi-layer electrical interconnect network comprising a plurality of interlayer dielectric layers, on the substrate;

selectively etching through the plurality of interlayer dielectric layers to expose an upper surface of the semiconductor active layer;

encapsulating the multi-layer electrical interconnect network with an inorganic capping layer that contacts the exposed upper surface of the semiconductor active layer, wherein said encapsulating comprises depositing an amorphous silicon capping layer at a temperature of less than about 350°

C. using a plasma-enhanced deposition technique;

selectively etching through the inorganic capping layer and the semiconductor active layer to expose the sacrificial layer; and

then

removing the sacrificial layer from the substrate to thereby suspend the semiconductor active layer from the substrate.

5. A method of forming an integrated circuit device, comprising:

forming a sacrificial layer on a handling substrate;

forming a semiconductor active layer on the sacrificial layer;

selectively etching through semiconductor active layer and the sacrificial layer in sequence to define a trench therein having a bottom adjacent the handling substrate;

filling the trench within an inorganic anchor;

selectively etching through the semiconductor active layer to thereby expose the sacrificial layer; and

removing the sacrificial layer from between the handling substrate and the semiconductor active layer to thereby suspend the semiconductor active layer from the inorganic anchor,

wherein said selectively etching through the semiconductor active layer to thereby expose the sacrificial layer is preceded by encapsulating the multi-layer electrical interconnect network with an inorganic capping layer.

6. The method of claim 5, wherein said selectively etching through the semiconductor active layer comprises selectively etching through the semiconductor active layer to define tethers extending between adjacent portions of the semiconductor active layer;

and wherein said removing comprises removing the sacrificial layer from between the handling substrate and the semiconductor active layer to thereby suspend the semiconductor active layer by the tethers.

7. The method of claim 5, further comprising forming the multi-layer electrical interconnect network on the semiconductor active layer.

8. The method of claim 5, further comprising forming the multi-layer electrical interconnect network on the semiconductor active layer after said selectively etching through the semiconductor active layer and the sacrificial layer.

9. The method of claim 5, wherein the inorganic anchor comprises polycrystalline silicon deposited using a low-pressure chemical vapor deposition (LPCVD) technique.

10. The method of claim 5, wherein said selectively etching through the semiconductor active layer to thereby expose the sacrificial layer comprises selectively etching through the inorganic capping layer and the semiconductor active layer in sequence to expose the sacrificial layer.

11. A method of forming an integrated circuit device, comprising:

selectively etching through a multi-layer electrical interconnect network to expose a semiconductor active layer;

encapsulating the multi-layer electrical interconnect network with an inorganic capping layer that contacts the semiconductor active layer;

selectively etching through the inorganic capping layer and the semiconductor active layer in sequence to expose a sacrificial layer extending between the semiconductor active layer and a handling substrate; and

removing the sacrificial layer to thereby suspend the semiconductor active layer and the encapsulated multi-layer electrical interconnect network opposite the handling substrate.

12. The method of claim 11, wherein the inorganic capping layer is a semiconductor capping layer.

13. The method of claim 12, wherein the inorganic capping layer is an amorphous silicon capping layer.

14. The method of claim 13, wherein said encapsulating is preceded by exposing the semiconductor active layer to a plasma etchant that roughens a surface of the semiconductor active layer.

15. The method of claim 14, wherein said exposing the semiconductor active layer to a plasma etchant follows said selectively etching through a multi-layer electrical interconnect network to expose a semiconductor active layer.