Oxide semiconductor, thin film transistor, and display device

• US 8,878,172 B2
• Filed: 10/19/2009
• Issued: 11/04/2014
• Est. Priority Date: 10/24/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ito, Shunichi, Sasaki, Toshinari, Hosoba, Miyuki, Sakata, Junichiro
• Primary Examiner(s): McCall Shepard, Sonya D
• Application Number:
  US12/581,187
• Publication Number:
  US 20100102311A1
• Time in Patent Office: 1,842 Days
• Field of Search: 257/43, 257/59, 257/E29.029, 257/E29.08, 257/635, 257/640, 257/E29.296
• US Class Current: 257/43
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to control composition and a defect of an oxide semiconductor, another object is to increase a field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with a reduced off current. A solution is to employ an oxide semiconductor whose composition is represented by InMO₃(ZnO)_m, where M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al, and m is preferably a non-integer number of greater than 0 and less than 1. The concentration of Zn is lower than the concentrations of In and M. The oxide semiconductor has an amorphous structure. Oxide and nitride layers can be provided to prevent pollution and degradation of the oxide semiconductor.

Claims

1. A thin film transistor comprising:

an oxide semiconductor layer;

a first silicon oxide layer and a second silicon oxide layer sandwiching the oxide semiconductor layer, each of the first silicon oxide layer and the second silicon oxide layer being in direct contact with the oxide semiconductor layer; and

a first nitride insulating layer and a second nitride insulating layer sandwiching a stack formed of the oxide semiconductor layer, the first silicon oxide layer and the second silicon oxide layer,

wherein the oxide semiconductor layer comprises O, In, Ga, and Zn, and wherein a concentration of Zn is comprised between 5 atomic % and 10 atomic %, and

wherein concentrations of In and Ga are each comprised between 15 atomic % and 20 atomic %.

2. The thin film transistor according to claim 1, wherein the oxide semiconductor layer has an amorphous structure.

3. A display device comprising the thin film transistor according to claim 1 in at least one pixel.

4. A display device comprising:

the thin film transistor according to claim 1 in at least one pixel; and

the thin film transistor according to claim 1 in a driver circuit for controlling a signal to be transmitted to the thin film transistor provided in the pixel.

5. A display device comprising:

the thin film transistor according to claim 1 in at least one pixel; and

the thin film transistor according to claim 1 in a selector circuit for controlling a signal to be transmitted to the thin film transistor provided in the pixel.

6. The thin film transistor according to claim 1, wherein the first nitride insulating layer and the second nitride insulating layer are silicon nitride layers.

7. The thin film transistor according to claim 1, further comprising a gate electrode layer,

wherein, when seen in cross-section along the channel formation region, the gate electrode layer has a larger width than the oxide semiconductor layer.

8. The thin film transistor according to claim 1, wherein the oxide semiconductor layer forms a channel formation region of the thin film transistor.

9. A thin film transistor comprising:

an oxide semiconductor layer;

a first silicon oxide layer and a second silicon oxide layer sandwiching the oxide semiconductor layer, each of the first silicon oxide layer and the second silicon oxide layer being in direct contact with the oxide semiconductor layer; and

a first nitride insulating layer and a second nitride insulating layer sandwiching a stack formed of the oxide semiconductor layer, the first silicon oxide layer and the second silicon oxide layer,

wherein the oxide semiconductor layer comprises O, In, Ga, and Zn.

10. The thin film transistor according to claim 9, wherein the first nitride insulating layer and the second nitride insulating layer are silicon nitride layers.

11. The thin film transistor according to claim 9, further comprising a gate electrode layer,

wherein, when seen in cross-section along the channel formation region, the gate electrode layer has a larger width than the oxide semiconductor layer.

12. The thin film transistor according to claim 9, wherein the oxide semiconductor layer has an amorphous structure.

13. A display device including the thin film transistor according to claim 9.

14. The thin film transistor according to claim 9, wherein the oxide semiconductor layer forms a channel formation region of the thin film transistor.

15. A thin film transistor comprising:

a gate electrode layer;

an oxide semiconductor layer;

a first silicon oxide layer and a second silicon oxide layer sandwiching the oxide semiconductor layer, each of the first silicon oxide layer and the second silicon oxide layer being in contact with the oxide semiconductor layer; and

a first nitride insulating layer and a second nitride insulating layer sandwiching a stack comprising the oxide semiconductor layer, the first silicon oxide layer, and the second silicon oxide layer,

wherein the first nitride insulating layer and the first silicon oxide layer are interposed between the gate electrode layer and the oxide semiconductor layer,

wherein the second nitride insulating layer is in contact with the second silicon oxide layer, and

wherein the oxide semiconductor layer comprises O, In, Ga, and Zn.

16. The thin film transistor according to claim 15, wherein the first nitride insulating layer and the second nitride insulating layer are silicon nitride layers.

17. The thin film transistor according to claim 15, wherein the oxide semiconductor layer has an amorphous structure.

18. A display device including the thin film transistor according to claim 15.

19. The thin film transistor according to claim 15, wherein the oxide semiconductor layer forms a channel formation region of the thin film transistor.

20. A thin film transistor comprising:

a gate electrode layer;

an oxide semiconductor layer;

a first silicon oxide layer and a second silicon oxide layer sandwiching the oxide semiconductor layer, each of the first silicon oxide layer and the second silicon oxide layer being in contact with the oxide semiconductor layer; and

a first nitride insulating layer and a second nitride insulating layer sandwiching a stack comprising the oxide semiconductor layer, the first silicon oxide layer, and the second silicon oxide layer,

wherein the first nitride insulating layer and the first silicon oxide layer are interposed between the gate electrode layer and the oxide semiconductor layer,

wherein, when seen in cross-section along the channel formation region, the gate electrode layer has a larger width than the oxide semiconductor layer, and

wherein the oxide semiconductor layer comprises O, In, Ga, and Zn.

21. A thin film transistor according to claim 20,

wherein the first nitride insulating layer and the first silicon oxide layer are interposed between the gate electrode layer and the oxide semiconductor layer.

22. A thin film transistor according to claim 20,

wherein the second nitride insulating layer is in contact with the second silicon oxide layer.

23. A thin film transistor according to claim 20,

wherein the first nitride insulating layer and the first silicon oxide layer are interposed between the gate electrode layer and the oxide semiconductor layer, and

wherein the second nitride insulating layer is in contact with the second silicon oxide layer.

24. The thin film transistor according to claim 20, wherein the first nitride insulating layer and the second nitride insulating layer are silicon nitride layers.

25. The thin film transistor according to claim 20, wherein the oxide semiconductor layer has an amorphous structure.

26. A display device including the thin film transistor according to claim 20.

27. The thin film transistor according to claim 20, wherein the oxide semiconductor layer forms a channel formation region of the thin film transistor.

28. A thin film transistor comprising:

an oxide semiconductor layer;

a first oxide insulating layer and a second oxide insulating layer sandwiching the oxide semiconductor layer, each of the first oxide insulating layer and the second oxide insulating layer being in direct contact with the oxide semiconductor layer; and

a first nitride insulating layer and a second nitride insulating layer sandwiching a stack formed of the oxide semiconductor layer, the first oxide insulating layer and the second oxide insulating layer.

29. The thin film transistor according to claim 28, wherein the oxide semiconductor layer forms a channel formation region of the thin film transistor.

30. The thin film transistor according to claim 28, wherein the oxide semiconductor layer has an amorphous structure.

31. The thin film transistor according to claim 28, further comprising a gate electrode layer,

wherein, when seen in cross-section along a channel formation region of the thin film transistor, the gate electrode layer has a larger width than the oxide semiconductor layer.

32. A display device including the thin film transistor according to claim 28.

33. A thin film transistor comprising:

an oxide semiconductor layer;

a first insulating layer and a second insulating layer each comprising oxygen and silicon sandwiching the oxide semiconductor layer, each of the first insulating layer and the second insulating layer being in direct contact with the oxide semiconductor layer; and

a third insulating layer and a fourth insulating layer each comprising nitrogen and sandwiching a stack formed of the oxide semiconductor layer, the first insulating layer and the second insulating layer.

34. The thin film transistor according to claim 33,

wherein the first insulating layer and the second insulating layer essentially consist of silicon and oxygen.

35. The thin film transistor according to claim 33,

wherein the third insulating layer and the fourth insulating layer essentially consist of nitrogen and silicon.

36. The thin film transistor according to claim 33, wherein the oxide semiconductor layer forms a channel formation region of the thin film transistor.

37. The thin film transistor according to claim 33, wherein the oxide semiconductor layer has an amorphous structure.

38. The thin film transistor according to claim 33, further comprising a gate electrode layer,

wherein, when seen in cross-section along a channel formation region of the thin film transistor, the gate electrode layer has a larger width than the oxide semiconductor layer.

39. A display device including the thin film transistor according to claim 33.