Semiconductor device and method for manufacturing semiconductor device

• US 8,878,177 B2
• Filed: 11/01/2012
• Issued: 11/04/2014
• Est. Priority Date: 11/11/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sasagawa, Shinya, Kurata, Motomu
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US13/666,150
• Publication Number:
  US 20130119375A1
• Time in Patent Office: 733 Days
• Field of Search: 257/43, 257/E29.255, 257/E21.46, 438/104
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02581 Transition metal or rare earth elements
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/34 the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445 , H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Provided is a miniaturized transistor having high electrical characteristics. The transistor includes a source electrode layer in contact with one side surface of the oxide semiconductor layer in the channel-length direction and a drain electrode layer in contact with the other side surface thereof. The transistor further includes a gate electrode layer in a region overlapping with a channel formation region with a gate insulating layer provided therebetween and a conductive layer having a function as part of the gate electrode layer in a region overlapping with the source electrode layer or the drain electrode layer with the gate insulating layer provided therebetween and in contact with a side surface of the gate electrode layer. With such a structure, an Lov region is formed with a scaled-down channel length maintained.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of:

forming an island-shaped oxide semiconductor layer;

forming a first conductive film covering the island-shaped oxide semiconductor layer;

removing the first conductive film in a region overlapping with the island-shaped oxide semiconductor layer by a chemical mechanical polishing method, and forming an opening in the first conductive film;

processing the first conductive film having the opening, and forming a source electrode layer and a drain electrode layer;

forming a gate insulating layer over the island-shaped oxide semiconductor layer, the source electrode layer, and the drain electrode layer;

forming a gate electrode layer over the gate insulating layer, wherein the gate electrode layer overlaps with the island-shaped oxide semiconductor layer;

introducing an impurity into the island-shaped oxide semiconductor layer using the gate electrode layer as a mask, and forming a first impurity region and a second impurity region in the island-shaped oxide semiconductor layer;

forming a second conductive film over the gate insulating layer and the gate electrode layer;

forming an insulating layer over the second conductive film;

processing the insulating layer, and forming a sidewall insulating layer in contact with a side surface of the second conductive film, wherein the sidewall insulating layer is not in contact with the gate electrode layer; and

etching the second conductive film using the sidewall insulating layer as a mask, and forming a conductive layer having a first portion in contact with a side surface of the gate electrode layer and a second portion in contact with an upper surface of the gate insulating layer.

2. The method for manufacturing the semiconductor device according to claim 1, wherein a side edge of the second portion is aligned with a side edge of the sidewall insulating layer.

3. The method for manufacturing the semiconductor device according to claim 1, wherein the conductive layer has an L-shape.

4. The method for manufacturing the semiconductor device according to claim 1, further comprising the steps of:

forming an interlayer insulating layer over the gate electrode layer, the sidewall insulating layer, and the gate insulating layer; and

forming a wiring over the interlayer insulating layer, wherein the wiring is in contact with the source electrode layer or the drain electrode layer through an opening provided in the interlayer insulating layer and the gate insulating layer.

5. The method for manufacturing the semiconductor device according to claim 1, wherein the island-shaped oxide semiconductor layer comprises a material selected from indium, gallium, and zinc.

6. The method for manufacturing the semiconductor device according to claim 1, wherein the conductive layer comprises the same material as the gate electrode layer.

7. The method for manufacturing the semiconductor device according to claim 1, wherein the island-shaped oxide semiconductor layer has a tapered shape.

8. The method for manufacturing the semiconductor device according to claim 1, wherein a thickness of the gate insulating layer in a region overlapping with the gate electrode layer is greater than a thickness of the gate insulating layer in a region overlapping with the conductive layer.

9. The method for manufacturing the semiconductor device according to claim 1, wherein a thickness of the gate insulating layer in a region overlapping with the conductive layer is greater than a thickness of the gate insulating layer in a region overlapping neither with the conductive layer nor with the gate electrode layer.

10. A method for manufacturing a semiconductor device comprising the steps of:

forming an island-shaped oxide semiconductor layer;

forming a first conductive film covering the island-shaped oxide semiconductor layer;

removing the first conductive film in a region overlapping with the island-shaped oxide semiconductor layer by a chemical mechanical polishing method, and forming an opening in the first conductive film;

processing the first conductive film having the opening, and forming a source electrode layer and a drain electrode layer;

forming a gate insulating layer over the island-shaped oxide semiconductor layer, the source electrode layer, and the drain electrode layer;

forming a gate electrode layer over the gate insulating layer, wherein the gate electrode layer overlaps with the island-shaped oxide semiconductor layer;

forming a second conductive film over the gate insulating layer and the gate electrode layer;

forming an insulating layer over the second conductive film;

processing the insulating layer, and forming a sidewall insulating layer in contact with a side surface of the second conductive film, wherein the sidewall insulating layer is not in contact with the gate electrode layer; and

etching the second conductive film using the sidewall insulating layer as a mask, and forming a conductive layer having a first portion in contact with a side surface of the gate electrode layer and a second portion in contact with an upper surface of the gate insulating layer.

11. The method for manufacturing the semiconductor device according to claim 10, wherein a side edge of the second portion is aligned with a side edge of the sidewall insulating layer.

12. The method for manufacturing the semiconductor device according to claim 10, wherein the conductive layer has an L-shape.

13. The method for manufacturing the semiconductor device according to claim 10, further comprising the steps of:

forming an interlayer insulating layer over the gate electrode layer, the sidewall insulating layer, and the gate insulating layer; and

forming a wiring over the interlayer insulating layer, wherein the wiring is in contact with the source electrode layer or the drain electrode layer through an opening provided in the interlayer insulating layer and the gate insulating layer.

14. The method for manufacturing the semiconductor device according to claim 10, wherein the island-shaped oxide semiconductor layer comprises a material selected from indium, gallium, and zinc.

15. The method for manufacturing the semiconductor device according to claim 10, wherein the conductive layer comprises the same material as the gate electrode layer.

16. The method for manufacturing the semiconductor device according to claim 10, wherein the island-shaped oxide semiconductor layer has a tapered shape.

17. The method for manufacturing the semiconductor device according to claim 10, wherein a thickness of the gate insulating layer in a region overlapping with the gate electrode layer is greater than a thickness of the gate insulating layer in a region overlapping with the conductive layer.

18. The method for manufacturing the semiconductor device according to claim 10, wherein a thickness of the gate insulating layer in a region overlapping with the conductive layer is greater than a thickness of the gate insulating layer in a region overlapping neither with the conductive layer nor with the gate electrode layer.