Semiconductor device and manufacturing method of the same

• US 8,878,262 B2
• Filed: 04/11/2012
• Issued: 11/04/2014
• Est. Priority Date: 05/13/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sakakura, Masayuki, Yamazaki, Shunpei
• Primary Examiner(s): KIM, SU C
• Application Number:
  US13/444,565
• Publication Number:
  US 20120248448A1
• Time in Patent Office: 937 Days
• Field of Search: 257/291, 257/443, 257/E21.434, 257/E21.453, 438/149, 349/52, 349/53
• US Class Current: 257/291
• CPC Class Codes: G02F 1/133302 Rigid substrates, e.g. inorganic substrates
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 3/2007 Display of intermediate tones
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 29/78663 Amorphous silicon transistors
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 2924/13069 : Thin film transistor [TFT]
• CPC Class Codes: H10K 59/1201 : Manufacture or treatment
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs
• CPC Class Codes: H10K 59/131 : Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/88 : Dummy elements, i.e. elements having non-functional features

Abstract

An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even in a case that the insulating film provided between adjacent pixels is formed by a coating method, there is a problem that thin portions are partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

Claims

1. A semiconductor device comprising:

a substrate;

a first wiring over the substrate;

a first insulating film over the first wiring;

a second wiring over the first insulating film;

a conductive layer over and in direct contact with the first insulating film, wherein the conductive layer comprises the same material as the second wiring;

a second insulating film over the conductive layer; and

a thin film transistor over the substrate, wherein the thin film transistor comprises a semiconductor layer and a portion of the first wiring,

wherein the conductive layer has a first region and a second region, wherein the first region overlaps with the first wiring and the second region does not overlap with the first wiring, and

wherein the conductive layer is electrically insulated from other wirings.

2. The semiconductor device according to claim 1, wherein the second wiring comprises a multi-layered film including a first metal layer and a second metal layer.

3. The semiconductor device according to claim 1, wherein an edge portion of each of the first wiring, the second wiring and the conductive layer has a tapered shape.

4. The semiconductor device according to claim 1, wherein the conductive layer does not overlap with the semiconductor layer.

5. The semiconductor device according to claim 1, wherein a thickness of the conductive layer is larger than that of a part of the second insulating film overlapping the conductive layer.

6. The semiconductor device according to claim 1, wherein the second insulating film over the first region and the second insulating film over the second region have substantially same thickness.

7. The semiconductor device according to claim 1, the semiconductor device further comprising a pixel electrode electrically connected to the thin film transistor.

8. The semiconductor device according to claim 1, wherein the thin film transistor comprises a part of the first wiring as a gate electrode, a part of the first insulating film as a gate insulating layer, and a part of the second wiring as a source electrode.

9. A display device comprising the semiconductor device according to claim 1.

10. A semiconductor device comprising:

a substrate;

a first wiring over the substrate;

a first insulating film over the first wiring;

a second wiring over the first insulating film;

a conductive layer over and in direct contact with the first insulating film, wherein the conductive layer comprises the same material as the second wiring;

a pixel electrode;

a second insulating film over the conductive layer; and

a thin film transistor over the substrate, wherein the thin film transistor comprises a semiconductor layer and is electrically connected to the pixel electrode,

wherein the conductive layer has a first region and a second region, wherein the first region overlaps with the first wiring and the second region does not overlap with the first wiring,

wherein the conductive layer is electrically insulated from other wirings, and

wherein a part of an edge portion of the conductive layer is parallel to a part of an edge portion of the pixel electrode.

11. The semiconductor device according to claim 10, wherein the second wiring comprises a multi-layered film including a first metal layer and a second metal layer.

12. The semiconductor device according to claim 10, wherein an edge portion of each of the first wiring, the second wiring and the conductive layer has a tapered shape.

13. The semiconductor device according to claim 10, wherein the conductive layer does not overlap with the semiconductor layer.

14. The semiconductor device according to claim 10, wherein a thickness of the conductive layer is larger than that of a part of the second insulating film overlapping the conductive layer.

15. The semiconductor device according to claim 10, wherein the second insulating film over the first region and the second insulating film over the second region have substantially same thickness.

16. The semiconductor device according to claim 10, wherein the pixel electrode is electrically connected to the thin film transistor.

17. The semiconductor device according to claim 10, wherein the thin film transistor comprises a part of the first wiring as a gate electrode, a part of the first insulating film as a gate insulating layer, and a part of the second wiring as a source electrode.

18. A display device comprising the semiconductor device according to claim 10.

19. A semiconductor device comprising:

a substrate;

a first wiring over the substrate;

a first insulating film over the first wiring;

a second wiring over the first insulating film;

a conductive layer over and in direct contact with the first insulating film, wherein the conductive layer comprises the same material as the second wiring;

a second insulating film over the conductive layer; and

a thin film transistor over the substrate, wherein the thin film transistor comprises a semiconductor layer and a portion of the first wiring,

wherein the conductive layer is electrically insulated from other wirings, and

wherein the conductive layer extends beyond an edge portion of the first wiring.

20. The semiconductor device according to claim 19, wherein the second wiring comprises a multi-layered film including a first metal layer and a second metal layer.

21. The semiconductor device according to claim 19, wherein an edge portion of each of the first wiring, the second wiring and the conductive layer has a tapered shape.

22. The semiconductor device according to claim 19, wherein the conductive layer does not overlap with the semiconductor layer.

23. The semiconductor device according to claim 19, wherein a thickness of the conductive layer is larger than that of a part of the second insulating film overlapping the conductive layer.

24. The semiconductor device according to claim 19, the semiconductor device further comprising a pixel electrode electrically connected to the thin film transistor.

25. The semiconductor device according to claim 19, wherein the thin film transistor comprises a part of the first wiring as a gate electrode, a part of the first insulating film as a gate insulating layer, and a part of the second wiring as a source electrode.

26. A display device comprising the semiconductor device according to claim 19.

27. A semiconductor device comprising:

a substrate;

a first wiring over the substrate;

a first insulating film over the first wiring;

a second wiring over the first insulating film;

a conductive layer over and in direct contact with the first insulating film, wherein the conductive layer comprises the same material as the second wiring;

a pixel electrode;

a second insulating film over the conductive layer; and

a thin film transistor comprising a portion of the first wiring over the substrate, wherein the thin film transistor comprises a semiconductor layer and is electrically connected to the pixel electrode,

wherein the conductive layer extends beyond an edge portion of the first wiring,

wherein the conductive layer is electrically insulated from other wirings, and

wherein a part of an edge portion of the conductive layer is parallel to a part of an edge portion of the pixel electrode.

28. The semiconductor device according to claim 27, wherein the second wiring comprises a multi-layered film including a first metal layer and a second metal layer.

29. The semiconductor device according to claim 27, wherein an edge portion of each of the first wiring, the second wiring and the conductive layer has a tapered shape.

30. The semiconductor device according to claim 27, wherein the conductive layer does not overlap with the semiconductor layer.

31. The semiconductor device according to claim 27, wherein a thickness of the conductive layer is larger than that of a part of the second insulating film overlapping the conductive layer.

32. The semiconductor device according to claim 27, wherein the pixel electrode is electrically connected to the thin film transistor.

33. The semiconductor device according to claim 27, wherein the thin film transistor comprises a part of the first wiring as a gate electrode, a part of the first insulating film as a gate insulating layer, and a part of the second wiring as a source electrode.

34. A display device comprising the semiconductor device according to claim 27.