Compact three dimensional vertical NAND and method of making thereof

• US 8,878,278 B2
• Filed: 01/30/2013
• Issued: 11/04/2014
• Est. Priority Date: 03/21/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Alsmeier, Johann, Makala, Raghuveer S., Costa, Xiying, Zhang, Yanli
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US13/754,293
• Publication Number:
  US 20130248974A1
• Time in Patent Office: 643 Days
• Field of Search: 257314-325, 257/E21.679, 257/27.103, 257/29.309
• US Class Current: 257/314
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates.

Claims

1. A NAND device, comprising:

an array of vertical NAND strings, wherein;

each NAND string comprises a semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, and a blocking dielectric located adjacent to the charge storage region;

at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate; and

the array comprises at least a 3×

3 array of NAND strings;

a plurality of control gate electrodes having a mesh shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level, wherein;

the first control gate electrode and the second control gate electrode are continuous in the array.

2. The device of claim 1, wherein the first control gate electrode and the second control gate electrode do not have an air gap or a dielectric filled trench in the array.

3. The device of claim 1, wherein:

each semiconductor channel has a pillar shape; and

the entire pillar-shaped semiconductor channel extends substantially perpendicularly to the major surface of the substrate.

4. The device of claim 1, wherein each NAND string in the array further comprises:

one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from above; and

another one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from below.

5. The device of claim 4, wherein each NAND string in the array further comprises:

an upper select gate electrode which is located adjacent to an upper portion of the pillar-shaped semiconductor channel above the first and the second control gate electrodes; and

a lower select gate electrode which is located adjacent to a lower portion of the pillar -shaped semiconductor channel below the first and the second control gate electrodes.

6. The device of claim 5, wherein:

each upper select gate electrode is separated from adjacent upper select gate electrodes in the array by an air gap or a dielectric filled trench; and

each lower select gate electrode is separated from adjacent lower select gate electrodes in the array by an air gap or a dielectric filled trench.

7. The device of claim 6, wherein:

each semiconductor channel comprises a first portion adjacent to the upper select gate electrode, a second portion adjacent to the lower select gate electrode, a third portion located in the first and the second device levels between the first and the second portions, and a landing pad portion located between the second and the third portions;

the third portion has a larger diameter or width than the first and the second portions; and

the landing pad portion has a larger diameter or width than the second and the third portions.

8. The device of claim 7, wherein:

the semiconductor channel comprises a solid rod shaped channel or a hollow cylinder shaped channel;

the tunnel dielectric comprises a cylinder which surrounds the semiconductor channel;

the charge storage region comprises a cylinder which surrounds the tunnel dielectric;

the blocking dielectric comprises a cylinder which surrounds the charge storage region; and

the first and the second control gate electrodes surround the blocking dielectric in each NAND string.

9. The device of claim 8, wherein the charge storage regions comprise a plurality of vertically spaced apart floating gates or a dielectric charge storage layer.

10. The device of claim 8, wherein:

the tunnel dielectric, the charge storage region and the blocking dielectric in each NAND string comprise a memory film; and

the semiconductor channels and memory films in the array are arranged in a substantially hexagonal pattern comprising a central semiconductor channel and memory film unit surrounded by six other semiconductor channel and memory film units arranged in a substantially hexagonal layout around the central semiconductor channel and memory film unit.

11. The device of claim 1, wherein:

the array comprises at least a 4×

6 array; and

the first control gate electrode and the second control gate electrode in the array are separated from respective first and second control gate electrodes in an adjacent array by an air gap or a dielectric filled trench.

12. The device of claim 11, further comprising a local interconnect which extends through the dielectric filled trench to contact a lower electrode located under the array.

13. A NAND device, comprising:

an array of vertical NAND strings, wherein;

each NAND string comprises a semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, and a blocking dielectric located adjacent to the charge storage region;

at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate; and

the array comprises at least a 3×

3 array of NAND strings;

a plurality of control gate electrodes having a mesh shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level, wherein;

the first control gate electrode and the second control gate electrode do not have an air gap or a dielectric filled trench in the array.

14. The device of claim 13, wherein the first control gate electrode and the second control gate electrode are continuous in the array.

15. The device of claim 13, wherein:

each semiconductor channel has a pillar shape; and

the entire pillar-shaped semiconductor channel extends substantially perpendicularly to the major surface of the substrate.

16. The device of claim 13, wherein each NAND string in the array further comprises:

one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from above; and

another one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from below.

17. The device of claim 16, wherein each NAND string in the array further comprises:

an upper select gate electrode which is located adjacent to an upper portion of the pillar-shaped semiconductor channel above the first and the second control gate electrodes; and

a lower select gate electrode which is located adjacent to a lower portion of the pillar -shaped semiconductor channel below the first and the second control gate electrodes.

18. The device of claim 17, wherein:

each upper select gate electrode is separated from adjacent upper select gate electrodes in the array by an air gap or a dielectric filled trench; and

each lower select gate electrode is separated from adjacent lower select gate electrodes in the array by an air gap or a dielectric filled trench.

19. The device of claim 18, wherein:

each semiconductor channel comprises a first portion adjacent to the upper select gate electrode, a second portion adjacent to the lower select gate electrode, a third portion located in the first and the second device levels between the first and the second portions, and a landing pad portion located between the second and the third portions;

the third portion has a larger diameter or width than the first and the second portions; and

the landing pad portion has a larger diameter or width than the second and the third portions.

20. The device of claim 19, wherein:

the semiconductor channel comprises a solid rod shaped channel or a hollow cylinder shaped channel;

the tunnel dielectric comprises a cylinder which surrounds the semiconductor channel;

the charge storage region comprises a cylinder which surrounds the tunnel dielectric;

the blocking dielectric comprises a cylinder which surrounds the charge storage region; and

the first and the second control gate electrodes comprise metal control gate electrodes which surround the blocking dielectric in each NAND string.

21. The device of claim 20, wherein the charge storage regions comprise a plurality of vertically spaced apart floating gates or a dielectric charge storage layer.

22. The device of claim 20, wherein:

the tunnel dielectric, the charge storage region and the blocking dielectric in each NAND string comprise a memory film; and

the semiconductor channels and memory films in the array are arranged in a substantially hexagonal pattern comprising a central semiconductor channel and memory film unit surrounded by six other semiconductor channel and memory film units arranged in a substantially hexagonal layout around the central semiconductor channel and memory film unit.

23. The device of claim 13, wherein:

the array comprises at least a 4×

6 array; and

the first control gate electrode and the second control gate electrode in the array are separated from respective first and second control gate electrodes in an adjacent array by an air gap or a dielectric filled trench.

24. The device of claim 23, further comprising a local interconnect which extends through the dielectric filled trench to contact a lower electrode located under the array.