Semiconductor device with enhanced mobility and method

• US 8,878,286 B2
• Filed: 05/15/2013
• Issued: 11/04/2014
• Est. Priority Date: 06/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Grivna, Gordon M., Hossain, Zia, Huang, Kirk K., Padmanabhan, Balaji, Robb, Francine Y., Venkatraman, Prasad
• Primary Examiner(s): Matthews, Colleen A
• Assistant Examiner(s): JOHNSON, CHRISTOPHER A
• Application Number:
  US13/895,197
• Publication Number:
  US 20130248982A1
• Time in Patent Office: 538 Days
• Field of Search: 257/328
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

Claims

1. A semiconductor device comprising:

a region of semiconductor material having a major surface;

a trench control structure in the region of semiconductor material including a gate dielectric layer adjacent sidewall surfaces of the trench control structure and a gate electrode comprising a first conductive material adjoining the gate dielectric layer;

a body region within the region of semiconductor material and adjacent the trench control structure, where the trench control structure is configured to provide a channel region within the body region, where the channel region includes a source end and a drain end;

a source region within the body region having a first side adjacent the trench control structure and a second side opposite to the first side; and

a first feature comprising a material other than the first conductive material encased completely within the gate electrode, where the first feature is configured to induce stress within portions of the channel region, and wherein the first feature comprises;

a base portion; and

a pair of side portions extending from the base portion.

2. The device of claim 1, where the first feature comprises dielectric material, and where the source end of the channel is vertically aligned with the drain end of the channel.

3. The device of claim 1, where the base portion is thicker than the side portions.

4. The device of claim 1, where the trench control structure further includes a shield electrode below the gate electrode, where the shield electrode is separated from the region of semiconductor material by a dielectric layer.

5. The device of claim 4 further comprising a second feature within the shield electrode, where the second feature is configured to induce stress within a drift region of the semiconductor device, and where at least one of the first and second features comprises a dielectric material.

6. The device of claim 1 further comprising a second feature adjoining the second side of the source region, where the second feature is configured to induce stress in proximity to the source end of the channel region.

7. The device of claim 1 further comprising second features adjacent to opposing corners of the gate electrode in proximity to the drain end of the channel region and configured to induce stress within the drain end of the channel region.

8. A semiconductor device structure comprising:

a region of semiconductor material having a first conductivity type, a first major surface, and a second major surface opposing the first major surface, where a portion of the region of semiconductor material is configured as a drain region;

a trench structure within the region of semiconductor material comprising a shield electrode in a lower portion of a trench, where the shield electrode is separated from the region of semiconductor material by a first dielectric layer;

a gate electrode formed in an upper portion of the trench, wherein the gate electrode is separated from the region of semiconductor material by a second dielectric layer and separated from the shield electrode by a third dielectric layer;

a body region having a second conductivity type opposite to the first conductivity type in the region of semiconductor material and adjacent to the trench structure, where the gate electrode is configured to form a channel region within the body region;

a source region of the first conductivity type in spaced relationship with the body region having a first side adjacent to the trench structure and a second side opposite to the first side;

a first feature within the gate electrode and comprising a material configured to propagate stress within the region of semiconductor material adjacent to the trench control structure;

a second feature within the shield electrode and comprising a material configured to propagate stress with the region of semiconductor material within a drift region of the structure; and

a third feature between the gate electrode and shield electrode and comprising a material configured to propagate stress within the region of semiconductor material proximate to a drain end of the channel region.

9. The structure of claim 8, where the third feature adjoins a surface of the gate electrode.

10. The structure of claim 8, where the third feature adjoins a surface of the shield electrode.

11. The structure of claim 8, where the first feature comprises a plurality of spaced-apart stripe-like shapes.

12. A semiconductor device comprising:

a region of semiconductor material having a first major surface;

a trench control structure in the region of semiconductor material including a gate dielectric layer adjacent sidewall surfaces of the trench control structure and a gate electrode comprising a first conductive material adjoining the gate dielectric layer;

a body region within the region of semiconductor material and adjacent the trench control structure, where the trench control structure is configured to provide a channel region within the body region;

a source region within the body region having a first side adjacent the trench control structure and a second side opposite to the first side; and

a first feature comprising a material other than the first conductive material within the gate electrode, where the first feature is configured to induce stress within portions of the channel region, and wherein the first feature comprises;

a base portion; and

a pair of side portions extending from the base portion, where a portion of the gate electrode is between opposing inner surfaces of the pair of side portions.

13. The device of claim 12, where the first feature comprises dielectric material, and where the device further comprises a first electrode electrically coupled to the source region proximate to the first major surface and a second electrode electrically coupled to the region of semiconductor material on a second major surface opposite to the first major surface.

14. The device of claim 12, where the base portion is thicker than the side portions.

15. The device of claim 12, where the first feature is embedded within the gate electrode.

16. The device of claim 12, where the trench control structure further includes a shield electrode below the gate electrode, where the shield electrode is separated from the region of semiconductor material by a dielectric layer.

17. The device of claim 16 further comprising a second feature within the shield electrode, where the second feature is configured to induce stress within a drift region of the semiconductor device, and where at least one of the first and second features comprises a dielectric material.

18. The device of claim 12 further comprising a second feature adjoining the second side of the source region, where the second feature is configured to induce stress in proximity to the source end of the channel region.

19. The device of claim 12 further comprising second features adjacent to opposing corners of the gate electrode in proximity to the drain end of the channel region and configured to induce stress within the drain end of the channel region.