Semiconductor device

• US 8,878,288 B2
• Filed: 04/13/2012
• Issued: 11/04/2014
• Est. Priority Date: 04/22/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Isobe, Atsuo, Sasaki, Toshinari
• Primary Examiner(s): STARK, JARRETT J
• Application Number:
  US13/446,026
• Publication Number:
  US 20120267709A1
• Time in Patent Office: 935 Days
• Field of Search: 257/57, 257/330, 257/E29.262
• US Class Current: 257/330
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

To provide a highly reliable semiconductor device. To provide a semiconductor device which prevents a defect and achieves miniaturization. An oxide semiconductor layer in which the thickness of a region serving as a source region or a drain region is larger than the thickness of a region serving as a channel formation region is formed in contact with an insulating layer including a trench. In a transistor including the oxide semiconductor layer, variation in threshold voltage, degradation of electric characteristics, and shift to normally on can be suppressed and source resistance or drain resistance can be reduced, so that the transistor can have high reliability.

Claims

1. A semiconductor device comprising:

a trench in an insulating layer;

a wide-gap semiconductor layer in contact with an uppermost surface of the insulating layer and an inner wall surface and a bottom surface of the trench;

a source electrode and a drain electrode electrically connected to the wide-gap semiconductor layer;

a gate insulating layer over the wide-gap semiconductor layer; and

a gate electrode over the gate insulating layer,

wherein each of a first thickness of the wide-gap semiconductor layer in contact with the inner wall surface and a second thickness of the wide-gap semiconductor layer in contact with the bottom surface is smaller than a third thickness of the wide-gap semiconductor layer in contact with the uppermost surface of the insulating layer, and

wherein the trench is filled with the gate electrode.

2. The semiconductor device according to claim 1, wherein an aspect ratio of the trench is greater than or equal to 0.5 and less than or equal to 5.0.

3. The semiconductor device according to claim 1, wherein the third thickness is greater than or equal to 1.5 times and less than or equal to 10 times as large as each of the first thickness and the second thickness.

4. The semiconductor device according to claim 1, wherein the wide-gap semiconductor layer is an oxide semiconductor layer.

5. A semiconductor device comprising:

a first transistor; and

a second transistor, the second transistor comprising;

a trench in an insulating layer;

a wide-gap semiconductor layer in contact with an uppermost surface of the insulating layer and an inner wall surface and a bottom surface of the trench;

a source electrode and a drain electrode electrically connected to the wide-gap semiconductor layer;

a gate insulating layer over the wide-gap semiconductor layer; and

a gate electrode over the gate insulating layer,

wherein the first transistor overlaps with at least a part of the second transistor,

wherein each of a first thickness of the wide-gap semiconductor layer in contact with the inner wall surface and a second thickness of the wide-gap semiconductor layer in contact with the bottom surface is smaller than a third thickness of the wide-gap semiconductor layer in contact with the uppermost surface of the insulating layer, and

wherein the trench is filled with the gate electrode.

6. The semiconductor device according to claim 5, wherein an aspect ratio of the trench is greater than or equal to 0.5 and less than or equal to 5.0.

7. The semiconductor device according to claim 5, wherein the third thickness is greater than or equal to 1.5 times and less than or equal to 10 times as large as each of the first thickness and the second thickness.

8. The semiconductor device according to claim 5, wherein an oxide semiconductor layer is used as the wide-gap semiconductor layer.