Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method

• US 8,878,292 B2
• Filed: 03/02/2008
• Issued: 11/04/2014
• Est. Priority Date: 03/02/2008
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Hbert, Franois, Bobde, Madhur, Bhalla, Anup
• Primary Examiner(s): Pizarro, Marcos D.
• Assistant Examiner(s): TANG, SUIAN
• Application Number:
  US12/074,280
• Publication Number:
  US 20090218619A1
• Time in Patent Office: 2,438 Days
• Field of Search: 257/E29.201, 257/E29.257, 257/E29.26, 257/218, 257329-331, 257/339, 257/341, 257/342
• US Class Current: 257/332
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

Claims

1. An accumulation mode field effect transistor (AccuFET) comprising:

trenched gates disposed in trenches opened in a top epitaxial layer on top of a bottom epitaxial layer both are doped with a first conductivity type wherein the top epitaxial layer having a higher dopant concentration and encompassing a source region near a top surface of a semiconductor substrate surrounding said trenched gates wherein each trenched gate is padded by a gate oxide layer and surrounded completely by regions of said first conductivity type including said source region and said top epitaxial layer of said first conductivity type and wherein said trenched gate includes a gate material of a second conductivity type filling the trenches and supporting a stick-up gate segment with the gate material extended above a top surface of said semiconductor substrate and the stick-up segment is surrounded by sidewall spacers disposed above the source region; and

slots opened in the top epitaxial layer between the sidewall spacers and parallel to and disposed at a distance away from said trenched gates wherein said slots extended into said top epitaxial layer of the first conductivity type and completely filled with the gate material doped with said second conductivity type and surrounded directly by said top epitaxial layer of said first conductivity type wherein said slots filled with said gate material contacting the source region laterally extended underneath the sidewall spacers from sidewalls of the trenched gates to the slots.

2. The accumulation mode field effect transistor of claim 1 wherein:

said stick-up gate segment further having a cap composed of an insulation material surrounded by said sidewall spacers.

3. The accumulation mode field effect transistor of claim 2 further comprising:

a layer of barrier metal covering a top surface of said cap and covering said sidewall spacers extending above a top surface of said slots.

4. The accumulation mode field effect transistor semiconductor power device of claim 1 further comprising:

a barrier metal layer composed of an ohmic metal layer covering a top surface of said slots to enhance an electrical contact between the source region and the gate material filled in the slots.

5. The accumulation mode field effect transistor semiconductor power device of claim 1 further comprising:

a plurality of accumulation mode field effect transistor (AccuFET) cells configured with a stripe layout.

6. The accumulation mode field effect transistor semiconductor power device of claim 1 further comprising:

a plurality of accumulation mode field effect transistor (AccuFET) cells configured with a closed cell layout.

7. An accumulation mode field effect transistor (AccuFET) comprising:

trenched gates disposed in trenches opened in a top epitaxial layer on top of a bottom epitaxial layer both are doped with a first conductivity type wherein the top epitaxial layer having a higher dopant concentration and encompassing a source region near a top surface of said top epitaxial layer surrounding said trenched gates wherein each trenched gate is padded by agate oxide layer and surrounded completely by regions of said first conductivity type including said source region and said top epitaxial layer of said first conductivity type and wherein said trenched gate includes a gate material of a second conductivity type filling the trenches; and

slots opened in the top epitaxial layer and parallel to and disposed at a distance away from said trenched gates wherein said slots extended into said top epitaxial layer of the first conductivity type completely filled with a conductive material of said second conductivity type and surrounded directly by said top epitaxial layer of said first conductivity type wherein the slots having a top surface substantially at a same level with the source region and in direct contact with the source region laterally extended from sidewalls of the trenched gates to the slots.

8. The accumulation mode field effect transistor of claim 7 wherein:

said trenched gate includes a stick-up gate segment with the gate material extended above a top surface of said semiconductor substrate and the stick-up segment is surrounded by sidewall spacers disposed above the source region.