Integrated circuit structure having a capacitor structured to reduce dishing of metal layers
First Claim
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1. An integrated circuit structure, comprising:
- a first area comprising at least one first type device that has a metal layer and a dielectric layer;
a second area comprising at least one second type device that has a metal layer and a dielectric layer;
wherein the metal layer of the first area has a first surface that defines a first plane, the metal layer of the second area has a second surface that defines a second plane, the dielectric layer of the first area has a third surface that defines a third plane, and the dielectric layer of the second area has a fourth surface that defines a fourth plane; and
a third area comprising at least one capacitor having an uppermost layer of polysilicon that has a surface that defines a fifth plane, and the capacitor having a dielectric layer that has a surface that defines a sixth plane,wherein the first, second, and fifth planes are coplanar and the third, fourth, and sixth planes are coplanar,wherein an area of the layer of polysilicon is greater than a sum of areas of the metal layers in the first and second areas, andwherein the third area is distributed among the first and second areas.
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Abstract
A method and integrated circuit structure for mitigating metal gate dishing resulting from chemical mechanical polishing. The integrated circuit structure comprises a first area comprising at least one first type device; a second area comprising at least one second type device; a third area comprising at least one capacitor having an uppermost layer of polysilicon, where the capacitor area is greater than a sum of the first and second areas. The method utilizes the polysilicon of the capacitor to mitigate metal gate dishing of a metal gate of at least one device.
66 Citations
15 Claims
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1. An integrated circuit structure, comprising:
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a first area comprising at least one first type device that has a metal layer and a dielectric layer; a second area comprising at least one second type device that has a metal layer and a dielectric layer; wherein the metal layer of the first area has a first surface that defines a first plane, the metal layer of the second area has a second surface that defines a second plane, the dielectric layer of the first area has a third surface that defines a third plane, and the dielectric layer of the second area has a fourth surface that defines a fourth plane; and a third area comprising at least one capacitor having an uppermost layer of polysilicon that has a surface that defines a fifth plane, and the capacitor having a dielectric layer that has a surface that defines a sixth plane, wherein the first, second, and fifth planes are coplanar and the third, fourth, and sixth planes are coplanar, wherein an area of the layer of polysilicon is greater than a sum of areas of the metal layers in the first and second areas, and wherein the third area is distributed among the first and second areas. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A integrated circuit structure, comprising:
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at least one first type device comprising a first metal electrode and a dielectric layer; at least one second type device comprising a second metal electrode and a dielectric layer; wherein the first metal electrode has a first surface that defines a first plane, the second metal electrode has a second surface that defines a second plane, the dielectric layer of the at least one first type device has a third surface that defines a third plane, and the dielectric layer of the at least one second type device has a fourth surface that defines a fourth plane; and at least one capacitor comprising a polysilicon layer having a surface that defines a fifth plane, wherein the first, second, and fifth planes are coplanar to enable uniform polishing of the first and second metal electrodes, and the capacitor having a dielectric layer that has a surface that defines a sixth plane, wherein the third, fourth, and sixth planes are coplanar, wherein the at least one capacitor is distributed among the first and second type devices. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification