High frequency probing structure

• US 8,878,560 B2
• Filed: 12/30/2010
• Issued: 11/04/2014
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hung, Wensen, Kuo, Ying-Hsin
• Primary Examiner(s): Nguyen, Tung X
• Assistant Examiner(s): LE, THANG XUAN
• Application Number:
  US12/982,541
• Publication Number:
  US 20120169367A1
• Time in Patent Office: 1,405 Days
• Field of Search: 324/756.03, 324/754.07, 324/755.01, 324/754.01, 324/754.03, 324/755.11, 298/40, 298/30, 298/53, 295/93, 296/030.9, 298/54
• US Class Current: 324/756.03
• CPC Class Codes: G01R 1/0408 Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808
• CPC Class Codes: G01R 1/06772 High frequency probes
• CPC Class Codes: G01R 1/07371 using an intermediate card or back card with apertures through which the probes pass
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/49167 with deforming of conductive path

Abstract

The present disclosure provide a probe card for wafer level testing. The probe card includes a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes various conductive lines having a first pitch on a first surface and a second pitch on a second surface, the second pitch being substantially less than the first pitch; a printed circuit board configured approximate the first surface of the space transformer; and a power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line of the space transformer to the printed circuit board.

Claims

1. A probe card for wafer level testing, comprising:

a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes various conductive lines having a first pitch on a first surface and a second pitch on a second surface, the second pitch being substantially less than the first pitch, with one or more embedded conductive plates within the space transformer and coupling the conductive lines having the first pitch with the conductive lines having the second pitch;

a printed circuit board configured approximate the first surface of the space transformer; and

a plurality of conductive plates disposed on the first surface of the space transformer and patterned to couple the power line and the ground line of the space transformer to the printed circuit board, the conductive plates having a greater contact area than a structure coupling the signal lines of the space transformer to the printed circuit board.

2. The probe card of claim 1, wherein the conductive plates include copper foil.

3. The probe card of claim 1, further comprising solder balls configured to couple the signal lines of the space transformer to the printed circuit board.

4. The probe card of claim 1, further comprising an additional power plane disposed on the printed circuit board and patterned to couple with the power line and the ground line of the space transformer.

5. The probe card of claim 1, further comprising a high frequency matching circuit formed on the space transformer and coupled with the power line and ground line of the space transformer.

6. The probe card of claim 1, further comprising an interposer disposed between the space transformer and the printed circuit board, the interposer for coupling the power and ground lines of the space transformer to the printed circuit board.

7. The probe card of claim 6, further comprising a flexible membrane circuit having:

a first end disposed between the printed circuit board and the interposer; and

a second end disposed between the space transformer and the interposer.

8. The probe card of claim 6, further comprising a flexible membrane circuit having:

a first end disposed between the space transformer and the interposer; and

a second end disposed on a top surface of the printed circuit board.

9. The probe card of claim 8, wherein the printed circuit board includes a through hole that the flexible membrane circuit passes through.

10. The probe card of claim 1, further comprising a plurality of needles configured to be aligned with bonding pads of multiple dies of a semiconductor wafer for multiple device testing in parallel.

11. A wafer test system, comprising:

a probe card designed to test a wafer, the probe card including;

a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes various conductive lines having a first pitch on a first surface and a second pitch on a second surface, the second pitch being substantially less than the first pitch,

a printed circuit board configured approximate the first surface of the space transformer, the printed circuit board having at least one hole therethrough, a flexible membrane circuit passing through the at least one hole, and

a first power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line to the printed circuit board, the first power plane comprising a conductive plate having a greater contact area than a structure coupling the signal lines of the space transformer to the printed circuit board;

a wafer prober designed to hold a wafer to be tested—

and control the probe card during a wafer test; and

a tester coupled to the probe card through a connection cable.

12. The wafer test system of claim 11, wherein the probe card further includes a second power plane formed on the printed circuit board and coupled with the first power plane.

13. The wafer test system of claim 11, wherein the probe card further comprises a high frequency matching circuit formed on the space transformer and coupled with the power line and ground line of the space transformer.

14. The wafer test system of claim 11, wherein the probe card further comprises an interposer disposed between the space transformer and the printed circuit board, the interposer for coupling the power and ground lines of the space transformer to the printed circuit board.

15. The wafer test system of claim 14, wherein the probe card further includes a flexible membrane circuit having:

a first end disposed between the printed circuit board and the interposer; and

a second end disposed between the space transformer and the interposer.

16. The wafer test system of claim 14, wherein the flexible membrane circuit comprises:

a first end disposed between the space transformer and the interposer; and

a second end disposed on a top surface of the printed circuit board.