Omnibus logic element

• US 8,878,567 B1
• Filed: 10/24/2013
• Issued: 11/04/2014
• Est. Priority Date: 03/25/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Pedersen, Bruce, Baeckler, Gregg, Lewis, David, Lee, Andy L., Kim, Henry, Schleicher, James, Yuan, Richard, Kaptanoglu, Sinan, Hutton, Mike, Saini, Rahul
• Primary Examiner(s): Cho, James H
• Application Number:
  US14/062,637
• Time in Patent Office: 376 Days
• Field of Search: 326 37- 49
• US Class Current: 326/41
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00
• CPC Class Codes: G06F 7/50 Adding; Subtracting G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence
• CPC Class Codes: H03K 19/017581 programmable
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Claims

1. An integrated circuit (IC) comprising:

a plurality of logic elements arranged in an array, each of the logic elements including;

an input-port component receiving a plurality of inputs,

a programmable logic function component including a first look-up table and a second look-up table sharing the plurality of inputs,

a fixed logic function component configured to perform an arithmetic function and coupled to at least one of the plurality of inputs, wherein the fixed logic component contains one or both of a binary adder function and a ternary adder function,

a register function component, and

means for programming the logic element to multiple different functional configurations using multiple different configurations of the input ports to generate multiple results at output ports of the logic element, wherein;

the logic element can be further configured to connect one or both of

(i) outputs of the programmable logic portion to inputs of the adder function; and

(ii) outputs of the programmable logic portion, along with signals taken from adjacent logic elements in the array, to the ternary adder function to perform ternary addition.

2. The IC of claim 1, wherein the register function of each logic element further comprises a register feedback mode wherein, for each logic element, the output of one of the register functions is fed back into one or more inputs of the logic element.

3. The IC of claim 1 where the signals from adjacent logic elements are dedicated connections.

4. The IC of claim 1 where the signals from adjacent logic elements are routed to additional input ports in the input region of the logic element and then the current logic element is configured to use these input ports for ternary addition.

5. The IC of claim 1, wherein each logic element is further configurable to implement a shift register between a first register and a second register in the logic element.

6. The IC of claim 1, wherein the register function component further comprises means for computing shift-register functions using an additional dedicated input and output to the logic elements respectively.

7. The IC of claim 1, wherein the register function component of the logic element contains two registers.

8. An integrated circuit (IC) comprising:

a plurality of logic elements arranged in an array, each of the logic elements including an input-port component receiving a plurality of inputs,

a programmable logic function component including a first look-up table and a second look-up table sharing the plurality of inputs,

a fixed logic function component,

a register function component, and

means for programming the logic element to multiple different functional configurations using multiple different configurations of the input ports to generate multiple results at output ports of the logic element, wherein

the programmable logic function component is an n-input lookup-table (LUT) containing 2ⁿ bits of LUT-mask; and

each logic element is configured to perform a plurality of logic functions, and wherein one of the logic functions performed by each logic element is an incomplete LUT function implementing a partial function of more than n inputs.

9. The IC of claim 8, wherein each logic element is configured to perform a plurality of logic functions, and wherein one of the logic functions performed by each logic element is a complete n-input lookup-table (LUT) using the entirety of the LUT-mask.

10. The IC of claim 8, wherein the number of input ports m is larger than n.

11. The IC of claim 8, wherein the LUT can be programmed to be fractured into two LUT functions each of size n−

1 or smaller using a combination of up to n independent and shared input ports to the logic element.

12. The IC of claim 8, wherein the LUT can be programmed to be fractured into two LUT functions of size n or smaller, using a combination of up to m independent and shared input ports to the logic element.

13. The IC of claim 12, wherein the LUT can be programmed to be fractured into the two LUT functions using exclusively independent input ports to the logic element.

14. The IC of claim 12, wherein the LUT can be programmed to be fractured into the two LUT functions using exclusively shared input ports to the logic element.

15. The IC of claim 12, wherein the logic functions performed by each logic function component further comprises configuring the logic element to implement two complete logic functions of n inputs using a combination of shared and independent inputs.