Interface circuit for driving fully-differential circuits

• US 8,878,587 B1
• Filed: 11/18/2013
• Issued: 11/04/2014
• Est. Priority Date: 07/18/2013
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Linear Technology Corporation (Analog Devices, Inc.)
• Inventors: Steensgaard-Madsen, Jesper
• Primary Examiner(s): Hernandez, William
• Application Number:
  US14/083,195
• Time in Patent Office: 351 Days
• Field of Search: 327/104, 327/306, 327/333, 327560-563, 330/252, 330/253, 330/258, 330/259
• US Class Current: 327/306
• CPC Class Codes: G05F 3/02 Regulating voltage or current
• CPC Class Codes: H03F 2203/45101 Control of the DC level being present
• CPC Class Codes: H03F 2203/45528 the FBC comprising one or more passive resistors and being coupled between the LC and the IC
• CPC Class Codes: H03F 3/45959 Controlling the input circuit of the differential amplifier
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/1295 Clamping, i.e. adjusting the DC level of the input signal to a predetermined value

Abstract

An interface circuit for driving a fully-differential circuit has a first circuit configured to decrease the voltage at its output in response to an increase in an average value of first and second input voltages. A first network receives the first input voltage and the output voltage of the first circuit to provide a first output voltage for driving the fully-differential circuit. A second network receives the second input voltage and the output voltage of the first circuit to provide a second output voltage for driving the fully-differential circuit. An impedance ratio of the first network is substantially matched to an impedance ratio of the second network.

Claims

1. An analog-to-digital converter (ADC) circuit including a fully-differential ADC and an interface circuit for driving the fully-differential ADC, the interface circuit being configured to receive a first input voltage and a second input voltage, and further configured to provide a first output voltage and a second output voltage, the interface circuit comprising:

a first circuit configured to receive the first and second input voltages, and provide a voltage at an output of the first circuit;

the first circuit is configured to decrease the voltage at the output of the first circuit in response to an increase in an average value of the first and second input voltages;

a first network configured to receive the first input voltage and the voltage at the output of the first circuit, and further configured to provide the first output voltage;

the first network being characterized by a first impedance ratio; and

a second network configured to receive the second input voltage and the voltage at the output of the first circuit, and further configured to provide the second output voltage;

the second network being characterized by a second impedance ratio substantially matched to the first impedance ratio.

2. A method of driving a fully-differential circuit using an interface circuit having a first circuit and first and second networks coupled to the first circuit, the method comprising the steps of:

providing the first circuit with first and second input voltages,

decreasing an output voltage of the first circuit in response to an increase in an average value of the first and second input voltages,

supplying the first input voltage and the output voltage of the first circuit to the first network to produce a first output voltage for driving a first input of the fully-differential circuit, and

supplying the second input voltage and the output voltage of the first circuit to the second network to produce a second output voltage for driving a second input of the fully-differential circuit,

wherein an impedance ratio of the first network is substantially matched to an impedance ratio of the second network.

3. An interface circuit for driving a fully-differential circuit, the interface circuit being configured to receive a first input voltage and a second input voltage, and further configured to provide a first output voltage and a second output voltage, the interface circuit comprising:

a regulator circuit configured to receive the first and second input voltages, and provide a regulator voltage at an output of the regulator circuit;

the regulator circuit is configured to decrease the regulator voltage at the output of the regulator circuit in response to an increase in an average value of the first and second input voltages;

a first network configured to receive the first input voltage and the regulator voltage, and further configured to provide the first output voltage;

the first network being characterized by a first impedance ratio; and

a second network configured to receive the second input voltage and the regulator voltage, and further configured to provide the second output voltage;

the second network being characterized by a second impedance ratio substantially matched to the first impedance ratio.

4. The circuit of claim 3, wherein the first impedance ratio substantially is a ratio of impedance values of two resistors included in the first network.

5. The circuit of claim 4, wherein the second impedance ratio substantially is a ratio of impedance values of two resistors included in the second network.

6. The circuit of claim 3, wherein the first output voltage is substantially equal to a weighted average of the first input voltage and the regulator voltage.

7. The circuit of claim 3, wherein the first impedance ratio is substantially equal to one.

8. The circuit of claim 3, wherein the first and second networks are interchangeable.

9. The circuit of claim 3, wherein the first and second networks are incorporated within a differential network.

10. The circuit of claim 3, wherein the first network includes a first resistor having a first terminal coupled to a first input node supplied by the first input voltage and having a second terminal coupled to a first output node at which the first output voltage is provided.

11. The circuit of claim 10, wherein the first network further includes a second resistor having a first terminal coupled to the second terminal of the first resistor and a second terminal coupled to a node at which the regulator voltage is provided.

12. The circuit of claim 11, wherein the second network includes a third resistor having a first terminal coupled to a second input node supplied with the second input voltage and having a second terminal coupled to a second output node at which the second output voltage is provided.

13. The circuit of claim 12, wherein the second network includes a fourth resistor having a first terminal coupled to the second terminal of the third resistor and a second terminal coupled to the node at which the regulator voltage is provided.

14. The circuit of claim 13, wherein the first impedance ratio is a ratio of impedance values of the first and second resistors, and the second impedance ratio is a ratio of impedance values of the third and fourth resistors.

15. The circuit of claim 3, wherein the regulator circuit is distinct from the first and second networks.

16. The circuit of claim 3, wherein the regulator circuit includes first and second input nodes for receiving the first and second input voltages, and an output node at which the regulator voltage is provided;

and the regulator circuit is coupled to the first and second networks only via the first and second input nodes and the output node.

17. The circuit of claim 3, wherein the regulator circuit comprises an operational amplifier and a third network characterized by a third impedance ratio which is substantially matched to the first and second impedance ratios.

18. The circuit of claim 17, wherein the third network is a substantially resistive network.

19. The circuit of claim 18, wherein the regulator circuit includes first and second input nodes for receiving the first and second input voltages, and an output node at which the regulator voltage is provided;

and the third network includes first and second resistors coupled between the first and second input nodes, and a third resistor coupled between a node connecting the first and second resistors and the output node.

20. The circuit of claim 19, wherein the third resistor is coupled between an inverting input and an output of the operational amplifier.

21. The circuit of claim 20, wherein an impedance value of the first resistor is substantially equal to an impedance value of the second resistor, which is substantially equal to two times an effective impedance value of a parallel configuration representing the first and second resistors.

22. The circuit of claim 21, wherein the third impedance ratio is a ratio of the effective impedance value and an impedance value of the third resistor.

23. The circuit of claim 3, wherein the interface circuit is configured to drive a fully-differential analog-to-digital converter.

24. The circuit of claim 23, wherein the fully-differential analog-to-digital converter is implemented on a semiconductor substrate shared with at least a portion of the interface circuit.

25. The circuit of claim 23, wherein the interface circuit and the fully-differential analog-to-digital converter are arranged in a shared package.

26. The circuit of claim 3, wherein a difference between the first and second output voltages is substantially independent of an average value of the first and second input voltages.

27. The circuit of claim 3, wherein a difference between the first and second output voltages is substantially independent of the regulator voltage provided by the regulator circuit.

28. The circuit of claim 3, wherein the regulator circuit is configured to receive a control voltage, and the regulator voltage provided by the regulator circuit is substantially a linear combination of the first and second input voltages and the control voltage.

29. The circuit of claim 28, wherein an average value of the first and second output voltages is substantially equal to the control voltage.

30. The circuit of claim 3, wherein the regulator circuit comprises a switched capacitor.

31. The circuit of claim 3, wherein an input impedance of the interface circuit is substantially resistive.