Variable phase amplifier circuit and method of use

• US 8,878,619 B2
• Filed: 12/19/2012
• Issued: 11/04/2014
• Est. Priority Date: 02/04/2009
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Sand 9, Inc. (Analog Devices, Inc.)
• Inventors: Badillo, Dean A., Schoepf, Klaus Juergen, Rebel, Reimund
• Primary Examiner(s): Johnson, Ryan
• Application Number:
  US13/720,560
• Publication Number:
  US 20130127534A1
• Time in Patent Office: 685 Days
• Field of Search: 331/116.R, 331/116.FE, 331/116.M, 331/154, 331/155, 331/156, 331/158, 331/135, 331/177.R, 331/177.V, 331/181, 331/107.A
• US Class Current: 331/116.R
• CPC Class Codes: H03B 5/30 with frequency-determining element being electromechanical resonator
• CPC Class Codes: H03F 3/45071 with semiconductor devices only
• CPC Class Codes: H03G 3/004 Control by varying the supply voltage
• CPC Class Codes: H03H 11/22 providing two or more phase shifted output signals, e.g. n-phase output

Abstract

A variable phase amplifier circuit is disclosed and its method of use in tuning devices having resonators. The variable phase amplifier receives an input differential signal pair. The input differential signal pair can be generated by a resonator device. The variable phase amplifier generates a modified differential signal pair in response to receiving the input differential signal pair. The variable phase amplifier provides a means to vary the phase of the modified differential signal pair with respect to the input differential signal pair, in an accurate and stable manner. If the modified differential signal pair with a phase shift introduced in it is fed back to the resonator device, the resonator will change its frequency of oscillation, where the new frequency of oscillation is a function of the phase of the modified differential signal pair.

Claims

1. A variable phase amplifier circuit comprising:

a phase splitter circuit, wherein the phase splitter circuit receives an input differential signal pair, and wherein the phase splitter circuit outputs a first and a second differential signal pair in response to receiving the input differential signal pair, and wherein the second differential signal pair has a phase that is different than a phase of the first differential signal pair;

a first variable gain amplifier circuit coupled to the phase splitter circuit, wherein the first variable gain amplifier circuit scales the first differential signal pair by a first scale factor in response to receiving the first differential signal pair;

a second variable gain amplifier circuit coupled to the phase splitter circuit, wherein the second variable gain amplifier circuit scales the second differential signal pair by a second scale factor in response to receiving the second differential signal pair;

and

a summation circuit coupled to the first and the second variable gain amplifier circuits, wherein the summation circuit receives a first and a second scaled differential signal pair from the first and the second variable gain amplifier circuits respectively, and outputs a modified differential signal pair in response;

wherein the first variable gain amplifier circuit comprises a limiter stage, wherein the limiter stage limits the amplitude of the first scaled differential signal pair.

2. The circuit of claim 1, wherein the phase of the first differential signal pair is the same as a phase of the input differential signal pair.

3. The circuit of claim 1, wherein a phase of the modified differential signal pair is a function of the first scale factor.

4. The circuit of claim 1, wherein the phase of the second differential signal pair is shifted 90 degrees with respect to the phase of the first differential signal pair.

5. The circuit of claim 4, wherein a phase of a second end of the first differential signal pair is shifted 180 degrees with respect to a phase of a first end of the first differential signal pair.

6. The circuit of claim 5, wherein a phase of a second end of the second differential signal pair is shifted 180 degrees with respect to a phase of a first end of the second differential signal pair.

7. The circuit of claim 6, wherein the phase of the modified differential signal pair is a function of the second scale factor.

8. The circuit of claim 7, wherein the first scale factor is different than the second scale factor.

9. The circuit of claim 8, wherein the phase of the modified differential signal pair is a function of the first and the second scale factors.

10. The circuit of claim 1, wherein the summation circuit sums a first end of the first scaled differential signal pair to a first end of the second scaled differential signal pair.

11. The circuit of claim 10, wherein the summation circuit sums a second end of the first scaled differential signal pair to a second end of the second scaled differential signal pair.

12. A method of adjusting a phase of a differential signal pair comprising:

phase splitting an input differential signal pair into a first differential signal pair and a second differential signal pair using a phase splitter circuit;

generating a first scaled differential signal pair, wherein generating a first scaled differential signal pair comprises scaling the first differential signal pair by a first scale factor;

generating a second scaled differential signal pair, wherein generating a second scaled differential signal pair comprises scaling the second differential signal pair by a second scale factor;

generating a modified differential signal pair, wherein generating a modified differential signal pair comprises summing the first and the second scaled differential signal pairs;

adjusting the first scale factor, wherein the phase of the modified differential signal pair is adjusted in response to adjusting the first scale factor;

limiting the amplitude of the first and the second differential signal pair;

and

adjusting the second scale factor, wherein a phase of the modified differential signal pair is adjusted in response to adjusting the second scale factor;

wherein a phase of the second differential signal pair is shifted 90 degrees with respect to a phase of the first differential signal pair; and

wherein a phase of a second end of the first differential signal pair is shifted 180 degrees with respect to a phase of a first end of the first differential signal pair; and

wherein a phase of a second end of the second differential signal pair is shifted 180 degrees with respect to a phase of a first end of the second differential signal pair.

13. The method of claim 12, wherein generating a modified differential signal pair comprises:

summing together a first end of the first scaled differential signal pair and a first end of the second scaled differential signal pair;

and

summing together a second end of the first scaled differential signal pair and a second end of the second scaled differential signal pair.