Display device and method for manufacturing the same

• US 8,879,011 B2
• Filed: 03/04/2014
• Issued: 11/04/2014
• Est. Priority Date: 08/27/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Sakata, Junichiro, Tsubuku, Masashi, Akimoto, Kengo, Hosoba, Miyuki, Sakakura, Masayuki, Oikawa, Yoshiaki
• Primary Examiner(s): Doan, Jennifer
• Application Number:
  US14/196,236
• Publication Number:
  US 20140186997A1
• Time in Patent Office: 245 Days
• Field of Search: 349/19, 349/33, 349/41, 349/42, 349/43, 349/49, 349/50
• US Class Current: 349/43
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over an insulating layer;

forming a source electrode layer and a drain electrode layer over and in contact with a first region of the oxide semiconductor layer;

forming an oxide insulating layer over and in contact with a second region of the oxide semiconductor layer; and

performing a heat treatment on the oxide insulating layer so that oxygen in the oxide insulating layer is supplied to the second region of the oxide semiconductor layer,

wherein a conductivity of the first region of the oxide semiconductor layer is higher than a conductivity of the second region of the oxide semiconductor layer.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of performing a heat treatment on the oxide semiconductor layer before the step of forming the oxide insulating layer.

3. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of performing a heat treatment on the oxide semiconductor layer under an atmosphere including nitrogen before the step of forming the oxide insulating layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, tin, and zinc.

6. The method for manufacturing a semiconductor device according to claim 1,

wherein the first region is an n-type region, and

wherein the second region is an i-type region.

7. The method for manufacturing a semiconductor device according to claim 1, wherein thickness of the oxide semiconductor layer is from 15 nm to 50 nm inclusive.

8. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device includes a field effect transistor, a liquid crystal display device, a television device, a mobile phone, a camera, a portable information terminal, or a personal computer.

9. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over an insulating layer;

performing a first heat treatment on the oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer over and in contact with a first region of the oxide semiconductor layer;

forming an oxide insulating layer over and in contact with a second region of the oxide semiconductor layer; and

performing a second heat treatment on the oxide insulating layer so that oxygen in the oxide insulating layer is supplied to the second region of the oxide semiconductor layer,

wherein a conductivity of the first region of the oxide semiconductor layer is higher than a conductivity of the second region of the oxide semiconductor layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the first heat treatment is performed before the steps of forming the source electrode layer, the drain electrode layer, and the oxide insulating layer.

11. The method for manufacturing a semiconductor device according to claim 9, wherein the first heat treatment is performed under an atmosphere including nitrogen.

12. The method for manufacturing a semiconductor device according to claim 9, wherein a temperature of the first heat treatment is higher than a temperature of the second heat treatment.

13. The method for manufacturing a semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

14. The method for manufacturing a semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises indium, tin, and zinc.

15. The method for manufacturing a semiconductor device according to claim 9,

wherein the first region is an n-type region, and

wherein the second region is an i-type region.

16. The method for manufacturing a semiconductor device according to claim 9, wherein thickness of the oxide semiconductor layer is from 15 nm to 50 nm inclusive.

17. The method for manufacturing a semiconductor device according to claim 9, wherein the semiconductor device includes a field effect transistor, a liquid crystal display device, a television device, a mobile phone, a camera, a portable information terminal, or a personal computer.