Semiconductor integrated circuit system and method for driving the same

• US 8,879,313 B2
• Filed: 06/05/2014
• Issued: 11/04/2014
• Est. Priority Date: 09/26/2011
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Park, Hae Chan, Kim, Soo Gil
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US14/297,243
• Publication Number:
  US 20140286090A1
• Time in Patent Office: 152 Days
• Field of Search: 365/46, 365/94, 365/100, 365/113, 365/129, 365/148, 365/163, 36518513-18533, 36518907-18912, 365/206, 365/222, 365/226, 36523003-23006, 257 2- 5, 257/9, 257/296, 257/310, 257/E21.35, 257/E31.047, 257/E27.006, 438/29, 438/95, 438/96, 438/166, 438/135, 438/240, 438/259, 438/365, 438/482, 438/486, 438/597, 438/785, 977/754
• US Class Current: 365/163
• CPC Class Codes: G11C 11/00 Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor G11C14/00 - G11C21/00 take precedence
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: Y10S 977/754 Dendrimer, i.e. serially branching or "tree-like" structure

Abstract

A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change compensation unit configured to restore the other of the first and second phase-change areas by compensating for a dummy phase-change caused in the other phase-change area due to a phase-change of the selected phase-change area.

Claims

1. A method of driving a semiconductor integrated circuit system, comprising:

phase-changing a selected memory cell area to a reset state;

detecting a phase-change resistance of a memory cell area adjacent to the selected memory cell area on the same phase-change line;

generating a correction current in response to a detection result of the phase-change resistance of the adjacent memory cell area; and

maintaining a phase-change state of the adjacent memory cell area by applying the correct current to the adjacent memory cell area.

2. The method of claim 1, wherein the phase-changing of the selected memory cell area includes applying a set current or a reset current to a bit line constituting the selected memory cell area.

3. The method of claim 1, wherein the applying of the correction current includes applying the correction current to a word line constituting the adjacent memory cell area.

4. The method of claim 3, wherein the correction current is applied as a signal pulsed at least once within a write enable period of the selected memory cell.

5. The method of claim 3, wherein the correction current is applied as a signal pulsed at least once immediately after a write enable period of the selected memory cell is terminated.