Direct multi-level cell programming

• US 8,879,322 B2
• Filed: 05/20/2014
• Issued: 11/04/2014
• Est. Priority Date: 08/29/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Marcu, Alon, Sharon, Eran, Alrod, Idan, Li, Yan, Oshinsky, Hadas
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US14/283,030
• Publication Number:
  US 20140254266A1
• Time in Patent Office: 168 Days
• Field of Search: 365/185.17, 365/185.33, 365/185.28
• US Class Current: 365/185.17
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices

Abstract

A data storage device includes a controller coupled to a non-volatile memory having a three-dimensional (3D) configuration. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage.

Claims

1. A method comprising:

in a data storage device that includes a controller coupled to a non-volatile memory having a three-dimensional (3D) configuration and circuitry associated with operation of memory cells of the non-volatile memory, the non-volatile memory including a group of storage elements, wherein each storage element includes a memory cell of the non-volatile memory that is configured to store multiple data bits, performing;

sending data from the controller to the non-volatile memory;

storing first bits corresponding to a first portion of the data into the group of storage elements during a first write stage, wherein each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage;

sending second bits corresponding to a second portion of the data to a second memory without sending the first bits to the second memory; and

retrieving the second bits from the second memory and storing at least the second bits into the group of storage elements during a second write stage.

2. The method of claim 1, further comprising, after storing the first bits into the group of storage elements, sending third bits corresponding to a third portion of the data to a third memory without sending the first bits to the third memory.

3. The method of claim 2, wherein the second memory is within the controller and wherein the third memory includes a single level cell (SLC) portion of the non-volatile memory.

4. The method of claim 2, wherein the second memory and the third memory are within the controller.

5. The method of claim 2, wherein the second memory and the third memory include a single level cell (SLC) portion of the non-volatile memory.

6. The method of claim 1, further comprising converting the data from a grey-type encoding to a binary-type encoding prior to sending the second bits to the second memory, and wherein the second bits are encoded according to the binary-type encoding.

7. The method of claim 1, wherein the data includes multiple logical pages, wherein the first portion of the data corresponds to a first logical page and wherein the second portion of the data corresponds to a second logical page.

8. The method of claim 7, wherein a third portion of the data corresponds to a third logical page, wherein third bits corresponding to the third logical page are retrievable from a third memory following completion of the first write stage, and wherein the second write stage stores information corresponding to the second bits and corresponding to the third bits.

9. The method of claim 8, wherein each storage element of the group of storage elements stores three bits upon completion of the second write stage and wherein the second write stage stores the second bits and the third bits into the group of storage elements by programming each storage element of the group of storage elements to a corresponding particular state of a set of states.

10. The method of claim 9, further comprising, after completion of the second write stage and after completion of another write stage to another group of cells, retrieving the third bits from the third memory and performing a third write stage to program each storage element to the corresponding particular state.

11. A data storage device comprising:

a controller; and

a non-volatile memory having a three-dimensional (3D) configuration and circuitry associated with operation of memory cells of the non-volatile memory, the non-volatile memory including a group of storage elements, wherein each storage element includes a memory cell of the non-volatile memory that is configured to store multiple data bits,

wherein the controller is configured to;

send data from the controller to the non-volatile memory;

store first bits corresponding to a first portion of the data into the group of storage elements during a first write stage, wherein each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage;

send second bits corresponding to a second portion of the data to a second memory without sending the first bits to the second memory; and

retrieve the second bits from the second memory and store at least the second bits into the group of storage elements during a second write stage.

12. The data storage device of claim 11, wherein, after storing the first bits into the group of storage elements, the controller is further configured to send third bits corresponding to a third portion of the data to a third memory without sending the first bits to the third memory.

13. The data storage device of claim 12, wherein the second memory is within the controller and wherein the third memory includes a single level cell (SLC) portion of the non-volatile memory.

14. The data storage device of claim 12, wherein the second memory and the third memory are within the controller.

15. The data storage device of claim 12, wherein the second memory and the third memory include a single level cell (SLC) portion of the non-volatile memory.

16. The data storage device of claim 11, wherein the data is converted from a grey-type encoding to a binary-type encoding prior to sending the second bits to the second memory and wherein the second bits are encoded according to the binary-type encoding.

17. The data storage device of claim 11, wherein the data includes multiple logical pages, wherein the first portion of the data corresponds to a first logical page and wherein the second portion of the data corresponds to a second logical page.

18. The data storage device of claim 17, wherein a third portion of the data corresponds to a third logical page, wherein third bits corresponding to the third logical page are retrievable from a third memory following completion of the first write stage, and wherein the second write stage stores information corresponding to the second bits and corresponding to the third bits.

19. The data storage device of claim 18, wherein each storage element of the group of storage elements stores three bits upon completion of the second write stage and wherein the second write stage stores the second bits and the third bits into the group of storage elements by programming each storage element of the group of storage elements to a corresponding particular state of a set of states.

20. The data storage device of claim 19, wherein after completion of the second write stage and after completion of another write stage to another group of cells, the controller is further configured to retrieve the third bits from the third memory and to perform a third write stage to program each storage element to the corresponding particular state.

21. A data storage device comprising:

a non-volatile memory having a three-dimensional (3D) configuration and circuitry associated with operation of memory cells of the non-volatile memory, the non-volatile memory including a group of storage elements, wherein each of the storage elements includes a memory cell of the non-volatile memory;

a set of latches configured to store data to be programmed to the group of storage elements during each particular stage of a multi-stage write operation; and

a second memory configured to store bits corresponding to one or more portions of the data between stages of the multi-stage write operation,

wherein the second memory is configured to receive the bits corresponding to the one or more portions of the data from the latches without receiving bits corresponding to a first portion of the data that is programmed to the group of storage elements during a first stage of the multi-stage write operation, and

wherein the latches are configured to receive the bits corresponding to the one or more portions of the data from the second memory and to receive the bits corresponding to the first portion of the data from the group of storage elements during a subsequent stage of the multi-stage write operation.

22. The data storage device of claim 21, further comprising mapping circuitry coupled to the latches, wherein the mapping circuitry is configured to modify the data in the latches prior to the first stage from a grey-type encoding to a binary-type encoding.

23. The data storage device of claim 22, wherein the mapping circuitry includes an exclusive-OR circuit to generate at least one value of the binary-type encoding of the data based on values of the grey-type encoding of the data.

24. The data storage device of claim 22, wherein the mapping circuitry is configured to perform a table lookup operation to determine at least one value of the binary-type encoding of the data based on values of the grey-type encoding of the data.