Flash memory with read tracking clock and method thereof

• US 8,879,332 B2
• Filed: 02/10/2012
• Issued: 11/04/2014
• Est. Priority Date: 02/10/2012
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Chung-Kuang, Chen, Han-Sung, Hung, Chun-Hsiung
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US13/370,833
• Publication Number:
  US 20130208544A1
• Time in Patent Office: 998 Days
• Field of Search: 365/185.25, 365/233.1, 365/189.07, 365/185.21
• US Class Current: 365/185.25
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

The configurations of a flash memory having a read tracking clock and method thereof are provided. The proposed flash memory includes a first and a second storage capacitors, a first current source providing a first current flowing through the first storage capacitor, a second current source providing a second current flowing through the second storage capacitor, and a comparator electrically connected to the first and the second current sources, and sending out a signal indicating a developing time being accomplished when the second current is larger than the first current.

Claims

1. A flash memory having a read tracking clock, comprising:

a current detecting circuit detecting a pre-charge time of the flash memory and comprising;

a copy circuit, comprising;

a reference current generator generating a reference current, and having a first terminal and a second terminal connected to a ground;

a first switch having a first terminal receiving a power supply voltage, a second terminal coupled to the first terminal of the reference current generator and generating a first charge current, and a control terminal receiving a first bit line clamping signal; and

a second switch having a first terminal receiving the power supply voltage, a second terminal generating a second charge current being a copy of the first charge current, and a control terminal receiving the first bit line clamping signal;

a mirror circuit reflecting the second charge current to a comparing circuit;

wherein and

the comparing circuit comparing the second charge current with a second reference current, and sending out a signal indicating the pre-charge time being accomplished when the second reference current is larger than the second charge current.

2. A flash memory according to claim 1 further comprising:

a first tracking circuit detecting a developing time of the flash memory, and comprising;

a first storage cell having a first terminal receiving a power supply voltage, a second terminal and a control terminal receiving a first bias,

a first storage capacitor having a first terminal electrically connected to the second terminal of the first storage cell and a second terminal connected to a ground;

a second storage cell having a first terminal receiving the power supply voltage, a second terminal and a control terminal receiving a second bias being a difference of the first bias and a predetermined value;

a first current source generating a first current flowing through the first storage capacitor when the first storage cell is conductive;

a second storage capacitor having a first terminal electrically connected to the second terminal of the second storage cell and a second terminal connected to the ground;

a second current source generating a second current flowing through the second storage capacitor when the second storage cell is conductive; and

a first comparator having an inverting terminal electrically connected to the first current source, a non-inverting terminal electrically connected to the second current source and an output terminal sending out a signal of the developing time being accomplished when the second current is larger than the first current.

3. A flash memory according to claim 2, wherein the copy circuit further comprises a first resistor and a third storage capacitor, each of which has a first and a second terminals, a third switch has a first terminal, a second terminal and a control terminal and a second comparator has an inverting terminal, a non-inverting terminal and an output terminal, the reference current generator further comprises a third terminal, the first terminal of the first resistor is electrically connected to the third terminal of the reference current generator, the second terminal of the first resistor is electrically connected to the first terminal of the third storage capacitor, the second terminal of the third storage capacitor is connected to the ground, the non-inverting terminal of the second comparator is electrically connected to the second terminal of the second switch and the first terminal of the third switch, the inverting terminal of the second comparator is electrically connected to the first terminal of the reference current generator, and the output terminal of the second comparator is electrically connected to the control terminal of the third switch.

4. A flash memory according to claim 3, wherein the mirror circuit comprises a fourth switch having a first terminal, a second terminal and a control terminal, the control terminal of the fourth switch is electrically connected to the first terminal of the fourth switch and the second terminal of the third switch, the second terminal of the fourth switch is connected to the ground, the comparing circuit comprises a fifth and a sixth switches, each of which has a first terminal, a second terminal and a control terminal, and an output terminal, the first terminal of the fifth switch receives the power supply voltage, the control terminal of the fifth switch receives a third bias, the second terminal of the fifth switch is electrically connected to the first terminal of the sixth switch and the output terminal and generates the second reference current, the second reference current is the first reference current multiplied by a factor, the control terminal of the sixth switch is electrically connected to the control terminal of the fourth switch, and the second terminal of the sixth switch is connected to the ground.

5. A flash memory according to claim 4 further comprising:

a sense amplifier having a latch;

a bit line connected with one of the first and the second storage capacitors at a storage capacitor node;

a third storage cell coupled to the bit line;

a third current source generating a third current flowing through the bit line and the storage capacitor node when the third storage cell is conductive;

a fourth storage capacitor having a first terminal electrically connected to the storage capacitor node and a second terminal connected to the ground; and

a second tracking circuit detecting a charge sharing time of the MBL and a strobe time; and

comprising;

a sense amplifier mimic circuit mimicking the sense amplifier for tracking the charge sharing time and a trigger point of the latch; and

a pulse generation circuit generating a strobe pulse signal according to the trigger point of the latch and tracking the strobe time according to the strobe pulse signal.

6. A flash memory according to claim 5, wherein the sense amplifier mimic circuit comprises a charge sharing node, a seventh switch to the eleventh switch, each of which has a first, a second and a control terminals, a first and a second inverters and a fifth storage capacitor, each of which has a first and a second terminals, wherein the control terminal of the seventh switch receives a second bit line clamping signal, the first terminal of the seventh switch is electrically connected to the second terminal of the eight switch, the second terminal of the seventh switch is electrically connected to the storage capacitor node, the control terminal of the eighth switch receives a fourth bias, the first terminal of the eighth switch receives the power supply voltage, the second terminal of the eighth switch is electrically connected to the first terminal of the fifth storage capacitor and the charge sharing node, the second terminal of the fifth storage capacitor is connected to the ground, the first terminal of the ninth switch receives the power supply voltage, the control terminal of the ninth switch is connected to the ground, the second terminal of the ninth switch is electrically connected to the first terminal of the tenth switch, the second terminal of the tenth switch is electrically connected to the first terminal of the eleventh switch and the first terminal of the first inverter, the control terminal of the tenth switch is electrically connected to the charge sharing node, the control terminal of the eleventh switch receives a fifth bias, the second terminal of the eleventh switch is connected to the ground, the first terminal of the second inverter is electrically connected to the second terminal of the first inverter, and a signal indicating the charge sharing time being accomplished is sent out when a potential value of the charge sharing node is changed from the power supply voltage to a relatively lower potential value of the storage capacitor node.

7. A flash memory according to claim 5, wherein the pulse generation circuit comprises a third to a sixth inverters and a sixth storage capacitor, each of which has a first and a second terminals, and a NAND gate having a first and a second input terminals and an output terminal, wherein the first terminal of the third inverter is electrically connected to the first terminal of the first inverter, the first terminal of the fourth inverter is electrically connected to the second terminal of the first inverter, the first terminal of the fifth inverter is electrically connected to the second terminal of the third inverter, the second terminal of the fifth inverter is electrically connected to the first input terminal of the NAND gate, the first terminal of the sixth inverter is electrically connected to the second terminal of the fourth inverter, the second terminal of the sixth inverter is electrically connected to the first terminal of the sixth storage capacitor and the second input terminal of the NAND gate, the second terminal of the sixth storage capacitor is connected to the ground, and the output terminal of the NAND gate outputs the strobe pulse signal.

8. A flash memory having a read tracking clock, comprising:

a first tracking circuit detecting a developing time of the flash memory, and comprising;

a first storage capacitor;

a first storage cell receiving a first bias and coupled to the first storage capacitor;

a second storage capacitor;

a second storage cell receiving a second bias and coupled to the second storage capacitor, wherein the second bias is the first bias subtracts a predetermined value;

a first current source generating a first current flowing through the first storage capacitor when the first storage cell is conductive;

a second current source generating a second current flowing through the second storage capacitor when the second storage cell is conductive; and

a first comparator having an inverting terminal electrically connected to the first current source, a non-inverting terminal electrically connected to the second current source and an output terminal sending out a signal indicating the developing time being accomplished when the second current is larger than the first current.

9. A flash memory according to claim 8 further comprising:

a current detecting circuit detecting a pre-charge time of the flash memory and comprising;

a copy circuit, comprising;

a reference current generator generating a reference current, and having a first terminal and a second terminal connected to a ground;

a first switch having a first terminal receiving a power supply voltage, a second terminal coupled to the first terminal of the reference current generator and generating a first charge current, and a control terminal receiving a first bit line clamping signal; and

a second switch having a first terminal receiving the power supply voltage, a second terminal generating a second charge current being a copy of the first charge current, and a control terminal receiving the first bit line clamping signal;

a mirror circuit reflecting the second charge current to the comparing circuit; and

a comparing circuit comparing the second charge current with a second reference current, and sending out a signal indicating the pre-charge time being accomplished when the second reference current is larger than the second charge current.

10. A flash memory according to claim 9 further comprising:

a sense amplifier having a latch;

a bit line connected with one of the first and the second storage capacitors at a storage capacitor node; and

a second tracking circuit detecting a charge sharing time of the storage capacitor node and a strobe time and comprising;

a sense amplifier mimic circuit mimicking the sense amplifier for tracking the charge sharing time and a trigger point of the latch, and comprising a charge sharing node, wherein a signal indicating the charge sharing time being accomplished is sent out when a potential value of the charge sharing node is changed from the power supply voltage to a relatively lower potential value of the storage capacitor node; and

a pulse generation circuit generating a strobe pulse signal according to the trigger point of the latch and tracking the strobe time according to the strobe pulse signal.

11. A flash memory according to claim 10, wherein the second tracking circuit is a charge sharing tracking circuit.

12. A flash memory according to claim 8, wherein the first tracking circuit is a developing time tracking circuit.

13. A method for a flash memory having a read tracking clock and a charge sharing node, comprising steps of:

detecting whether a voltage value of the charge sharing node is decreased; and

if it is, sending out a signal indicating a charge sharing time being accomplished.

14. A method according to claim 13, wherein the flash memory further comprises a sense amplifier mimic circuit, and the detecting step further comprises steps of:

providing an input current of the sense amplifier mimic circuit; and

generating a corresponding read tracking clock by utilizing the input current and coping with the sense amplifier mimic circuit.

15. A method according to claim 13, wherein the flash memory further comprises a sense amplifier, and the detecting step further comprises steps of:

providing an input current of the sense amplifier; and

generating a corresponding read tracking clock by utilizing the input current and coping with the sense amplifier.