Non-volatile memory bank and page buffer therefor

• US 8,879,351 B2
• Filed: 09/14/2012
• Issued: 11/04/2014
• Est. Priority Date: 11/27/2006
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US13/618,022
• Publication Number:
  US 20130044543A1
• Time in Patent Office: 781 Days
• Field of Search: 365/189.05, 365/230.06, 365/230.08, 365/239
• US Class Current: 365/230.06
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 2216/20 Suspension of programming or erasing cells in an array in order to read other cells in it
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1033 using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/1048 : Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/12 : Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. Each half of the memory bank is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

Claims

1. A page buffer of a memory bank having a memory array coupled to bitlines and wordlines, the page buffer comprising:

first and second page buffer sections,

the first page buffer section comprising a first enabler and a first page buffer segment coupled to first bitlines and datelines and configured to access the first bitlines,

the second page buffer section comprising a second enabler and a second page buffer segment coupled to second bitlines and the datelines and configured to access the second bitlines,

the first enabler being configured;

to receive an input column select signal; and

to provide

an output column select signal in response to a clock signal, the output column select signal being derived from the input column select signal, and

a first enable signal to the first page buffer segment in response to the input column select signal, the first enable signal enabling column selection of the first page buffer segment,

the second enabler being configured;

to receive the output column select signal from the first enabler as an input column select signal thereof, and

to provide a second enable signal to the second page buffer segment in response to the input column select signal thereof, the second enable signal enabling column selection of the second page buffer segment.

2. The page buffer of claim 1, wherein:

the first page buffer segment of the first page buffer section is configured

to sense data from the first bitlines and

to provide the sensed data to the datelines in response to the column selection enabled by the first enable signal; and

the second page buffer segment of the second page buffer section is configured

to sense data from the second bitlines, and

to provide the sensed data to the datelines in response to the column selection enabled by the second enable signal.

3. The page buffer of claim 1, wherein:

the first enabler is configured to provide the first enable signal to the first page buffer segment in response to the input column select signal latched in a state of the clock signal; and

the second enabler is configured to provide the second enable signal to the second buffer segment in response to the input column select signal latched in a subsequent state of the clock signal, the input column select signal of the second enabler being a delayed version of the input column select signal received by the first enabler.

4. The page buffer of claim 3, wherein:

the first enabler comprises;

an input terminal for receiving the input column select signal, the input column select signal being latched in response to the complement state of the clock signal;

an output terminal for outputting the output column select signal in response to the latched input column select signal and to the clock signal; and

a column select output for providing the first enable signal having a logic state corresponding to the column select signal during the state of the clock signal, and

the second enabler comprises;

an input terminal for receiving the input column select signal, the input column select signal being latched in response to the complement state of the clock signal; and

a column select output for providing the second enable signal having a logic state corresponding to the column select signal during the subsequent state of the clock signal.

5. The page buffer of claim 3, wherein each of the first and second page buffer segments comprises one or more page buffer units, one page buffer unit being coupled to at least one of the respective bitlines and corresponding at least one of the datelines,

at least one of the page buffer units of the first page buffer segment being enabled in response to the first enable signal,

at least one of the page buffer units of the second page buffer segment being enabled in response to the second enable signal.

6. The page buffer of claim 5, wherein:

the one page buffer unit of the first page buffer segment comprises

first sense circuitry configured to sense data of one of the first bitlines, and

a first coupling circuit configured to couple the sensed data from the first sense circuitry to the corresponding dataline in response to the first enable signal; and

the one page buffer unit of the second page buffer segment comprises

second sense circuitry configured to sense data of one of the second bitlines, and

a second coupling circuit configured to couple the sensed data from the second sense circuitry to the corresponding dataline in response to the second enable signal.

7. The page buffer of claim 2, wherein the first enabler comprises bi-stable circuitry clocked by the clock signal having the state and a complement state, the bi-stable circuitry configured:

to receive the input column select signal at the input terminal and latch it in response to the complement state of the clock signal;

to provide the output column select signal through the output terminal in response to the clock signal; and

to provide the first enable signal having a logic state corresponding to the column select signal through the column select output during the state of the clock signal.

8. The page buffer of claim 7, wherein the bi-stable circuitry comprises a master/slave circuit including:

first and second cross-coupled inverters coupled to first and second reset devices, respectively, which are configured to respond to a control signal and a complementary control signal, respectively;

first and second transmission gates configured to respond to a state of the clock signal and a complement state of the clock signal, respectively, the second transmission gate being configured to transmit the logic state of the first cross-coupled inverters to the second cross-coupled inverters; and

a logic circuit configured to provide the enable signal in response to the logic status of the second cross-coupled inverters and a decode enable signal.

9. The page buffer of claim 6, wherein:

the first sense circuitry comprises a first sensor configured to sense the data of one of the first bitlines, and

the first coupling circuit comprises a first coupling device configured to couple the sensor to the corresponding dataline in response to the first enable signal;

the second sense circuitry comprises a second sensor configured to sense the data of one of the second bitlines, and

the second coupling circuit comprises a second coupling device configured to couple the sensor to the corresponding dataline in response to the second enable signal.

10. The page buffer of claim 6, wherein each of the first and second coupling circuits comprises a data provider configured to provide the sensed data from the first and the second sense circuitry to the corresponding data line in response to the respective enable signal.

11. The page buffer of claim 1, wherein each of the first and second page buffer sections forms a self-decoding page buffer stage that is arranged for sensing data from a set of bitlines and providing sensed data, the page buffer being used for at least one of read and program operations of a non-volatile memory.

12. A method for accessing a memory bank having a memory array coupled to bitlines and wordlines, the method comprising:

at the first page buffer section

receiving an input column select signal;

outputting an output column select signal derived from the input column select signal in response to a clock signal,

outputting a first enable signal in response to the input column select signal, and

at the second page buffer section

receiving the output column select signal of the first page buffer section as an input column select signal thereof, and

outputting a second enable signal in response to the input column select signal; and

enabling column selection of the first and the second page buffer segments in response to the first and the second enable signals, respectively.

13. The method of claim 12, further comprising:

sensing data from first and second bitlines; and

latching the sensed data from the first and the second bitlines in response to the enabling column selection of the first and the second page buffer segments.

14. The method of claim 13, further comprising:

sequentially outputting the latched data from the first and the second page buffer sections to datelines in each clock cycle in response to the input column select signal and an enable signal.

15. The method of claim 14, wherein for each of the first and the second page buffer sections, the sequentially outputting comprises:

shifting the column select signal to each of the plural first and second page buffer sections in each clock cycle.

16. The method of claim 15, wherein the shifting including:

receiving the column select signal on a first clock signal transition of a first clock cycle; and

latching and outputting the column select signal to a subsequent page buffer section on a second clock signal transition of the first clock cycle.