Differential power analysis—resistant cryptographic processing

• US 8,879,724 B2
• Filed: 12/14/2009
• Issued: 11/04/2014
• Est. Priority Date: 01/02/1998
• Status: Expired due to Fees

• Current Assignee: Cryptography Research, Inc. (Rambus Inc.)
• Original Assignee: Rambus Inc.
• Inventors: Kocher, Paul C., Jaffe, Joshua M., Jun, Benjamin C.
• Primary Examiner(s): Barron, Jr., Gilberto
• Assistant Examiner(s): Nobahar, Abdulhakim
• Application Number:
  US12/637,565
• Publication Number:
  US 20100091982A1
• Time in Patent Office: 1,786 Days
• Field of Search: 726/9, 726/20, 726/22, 726/25, 713/159, 713/172, 713/185, 713/189, 713/193, 713/194, 713/300, 713/310, 713322-324, 713/340, 713/400, 713/401, 713500-503, 713/600, 713/601, 380/1, 380/28, 380/29, 380204-207, 380/218, 380252-254
• US Class Current: 380/1
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: G06F 2207/7223 Randomisation as countermeasure against side channel attacks
• CPC Class Codes: G06F 2207/7266 Hardware adaptation, e.g. dual rail logic; calculate add and double simultaneously
• CPC Class Codes: G06F 7/00 Methods or arrangements for processing data by operating upon the order or content of the data handled logic circuits H03K19/00
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 19/07363 by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/382 insuring higher security of transaction
• CPC Class Codes: G06Q 20/409 Device specific authentication in transaction processing
• CPC Class Codes: G07F 7/08 by coded identity card or credit card or other personal identification means without personal verification means G07F7/02
• CPC Class Codes: G07F 7/082 Features insuring the integrity of the data on or in the card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/04 Masking or blinding
• CPC Class Codes: H04L 2209/08 Randomization, e.g. dummy operations or using noise
• CPC Class Codes: H04L 2209/56 Financial cryptography, e.g. electronic payment or e-cash
• CPC Class Codes: H04L 2209/805 : Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor
• CPC Class Codes: H04L 9/003 : for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/0618 : Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation

Abstract

Information leaked from smart cards and other tamper resistant cryptographic devices can be statistically analyzed to determine keys or other secret data. A data collection and analysis system is configured with an analog-to-digital converter connected to measure the device'"'"'s consumption of electrical power, or some other property of the target device, that varies during the device'"'"'s processing. As the target device performs cryptographic operations, data from the A/D converter are recorded for each cryptographic operation. The stored data are then processed using statistical analysis, yielding the entire key, or partial information about the key that can be used to accelerate a brute force search or other attack.

Claims

1. A cryptographic processing device for securely performing a cryptographic processing operation in a manner resistant to discovery of a secret by external monitoring of variations in the amount of power consumed, comprising:

(a) an input interface for receiving a quantity to be processed;

(b) a source of unpredictable information;

(c) a processor for performing said cryptographic processing operation in a manner decorrelated from externally-monitorable signals produced by said device, by using outputs from said source to select between operating on an instruction and inserting a delay before operating on said instruction, wherein inserting said delay includes performing a no-operation processor instruction prior to said cryptographic processing operation, said selection being based on a determination of whether the received quantity is to be processed cryptographically; and

(d) an output interface for providing said processed quantity to a recipient thereof.

2. The device of claim 1 embodied as a smartcard.

3. The device of claim 1 where said use of said unpredictable information in selecting in (c) causes said device to have unpredictable variations in power consumption.

4. A method of securely performing a cryptographic processing operation in a manner resistant to information leakage attacks, using a cryptographic processing device that consumes power and produces externally monitorable signals, comprising:

(a) receiving a quantity to be processed;

(b) generating unpredictable information;

(c) determining whether to process the received quantity cryptographically; and

(d) based on the determination, cryptographically processing said quantity, including using said unpredictable information to conceal a correlation between externally-monitorable signals produced by said device and said processing by selecting between operating on an instruction and inserting a delay before operating on said instruction, wherein said delay insertion includes a no-operation processor instruction.

5. The method of claim 4 where said delaying operation uses unpredictable information to consume a varying amount of power.