Debugging a memory subsystem

• US 8,880,779 B2
• Filed: 08/05/2011
• Issued: 11/04/2014
• Est. Priority Date: 08/05/2011
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Fai, Anthony, Wakrat, Nir Jacob, Seroff, Nicholas
• Primary Examiner(s): CHOE, YONG J
• Application Number:
  US13/204,037
• Publication Number:
  US 20130036254A1
• Time in Patent Office: 1,187 Days
• Field of Search: 711/103, 711/E12.008
• US Class Current: 711/103
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Abstract

In one implementation, a memory subsystem includes non-volatile memory, a memory controller that is communicatively connected to the non-volatile memory over a first bus, a host interface through which the memory controller communicates with a host controller over a second bus, and a joint test action group (JTAG) interface that provides the host controller with access to state information associated with the memory controller. The memory subsystem can be configured to be coupled to a board-level memory device that includes the host controller.

Claims

1. A memory subsystem comprising:

non-volatile memory;

a memory controller coupled to the non-volatile memory via a first bus;

a host interface coupled to a host controller via a second bus, wherein the host interface is configured to receive commands to be executed by the memory controller from the host controller; and

a joint test action group (JTAG) interface coupled to the host controller via a third bus, wherein the JTAG interface is configured to;

provide state information associated with the memory controller to the host controller responsive to a request from the host controller;

receive input test data from the host controller via the third bus;

send the input test data to the non-volatile memory via the first bus;

retrieve output data from the non-volatile memory via the first bus; and

send the output test data to the host controller via the third bus;

wherein the memory subsystem is configured to be coupled to a board-level memory device that includes the host controller.

2. The memory subsystem of claim 1, further comprising one or more debug modules that control operation of the memory controller based on instructions received from the host controller through the JTAG interface.

3. The memory subsystem of claim 2, wherein the instructions received through the JTAG interface specify a debug mode according to which the debug modules control operation of the memory controller.

4. The memory subsystem of claim 3, wherein the debug mode causes the debug modules to halt operation of the memory controller when the memory controller reaches one or more identified breakpoints in a series of instructions being executed by the memory controller.

5. The memory subsystem of claim 3, wherein the debug mode causes the debug modules to trace operation of the memory subsystem, wherein tracing operation of the memory subsystem includes, at least, outputting information indicating instructions executed by the memory subsystem through the JTAG interface.

6. The memory subsystem of claim 1, wherein the state information includes one or more current register values.

7. The memory subsystem of claim 1, wherein the state information includes information indicating one or more instructions being performed by the memory controller.

8. The memory subsystem of claim 1, wherein the state information includes data being transmitted over the first bus or the second bus.

9. The memory subsystem of claim 1, wherein the memory subsystem is a flash memory package and the non-volatile memory includes flash memory.

10. The memory subsystem of claim 9, wherein the flash memory includes one or more NAND flash memory dies.

11. The memory subsystem of claim 1, wherein the memory subsystem is limited to performing memory operations as directed by the host controller, and wherein the host controller performs input and output operations for the board-level memory device.

12. A system comprising:

a host controller of a board-level memory device; and

one or more memory subsystems of the board-level memory device that are accessible by the host controller over a plurality of buses, each of the memory subsystems including;

non-volatile memory;

a memory controller coupled to the non-volatile memory via a first bus of the plurality of buses;

a host interface coupled to a host controller over a second bus, wherein the host interface is configured to receive commands to be executed by the memory controller from the host controller; and

a Joint Test Action Group (JTAG) interface coupled to the host controller via a third bus of the plurality of buses, wherein the JTAG interface is configured to;

provide state information associated with the memory subsystem to the host controller responsive to a request form the host controller;

receive input test data from the host controller via the third bus;

send the input test data to the non-volatile memory via the first bus;

retrieve output test data from the non-volatile memory via the first bus; and

send the output test data to the host controller via the third bus.

13. The system claim 12, wherein each of the memory subsystems the further includes one or more debug modules that control operation of the memory controller based on instructions received from the host controller through the JTAG interface.

14. The system of claim 13, wherein the instructions received through the JTAG interface specify a debug mode according to which the debug modules control operation of the memory controller.

15. The system of claim 14, wherein the debug mode includes a halt mode that causes operation of the memory controller to be halted while the state information is obtained.

16. The system of claim 14, wherein the debug mode includes a monitor mode that causes one or more operations performed by memory controller to be performed and monitored by the debug modules.

17. The system of claim 12, wherein the state information includes one or more current register values.

18. The system of claim 12, wherein the state information includes one or more instructions being performed by the memory controller.

19. The system of claim 12, wherein the state information includes information being transmitted over one or more internal busses of the memory subsystem.

20. The system of claim 12, wherein the memory subsystem is a flash memory package and the non-volatile memory includes flash memory.

21. The system of claim 20, wherein the flash memory includes one or more NAND flash memory dies.

22. The system of claim 12, wherein the memory subsystem is limited to performing memory operations as directed by the host controller, and wherein the host controller performs input and output operations for the board-level memory device.

23. A method comprising:

receiving, at a host interface of a memory controller of a memory subsystem, commands to be executed by the memory controller from a host controller, wherein the host interface is coupled to the host controller via a second bus, and wherein the memory controller is coupled to non-volatile memory via a first bus;

receiving, at the memory controller through a Joint Test Action Group (JTAG) interface of the memory subsystem, a command from the host controller to obtain status information for the memory subsystem and input test data, wherein the JTAG interface is coupled to the host controller via a third bus;

sending the input test data to non-volatile memory via the first bus;

retrieving output test data from the non-volatile memory via the first bus;

sending the output test data to host controller;

accessing the state information during operation of the memory subsystem; and

providing the status information to the host controller, wherein the memory subsystem is coupled to a board-level memory device that includes the host controller.

24. The method of claim 23, wherein the state information is accessed using a debug module that controls operation of the memory controller based on the command received from the host controller through the JTAG interface.

25. The method of claim 24, wherein the command received through the JTAG interface specifies a debug mode according to which the debug modules control operation of the memory controller.

26. The method of claim 25, wherein the debug mode includes a halt mode that causes operation of the memory controller to be halted while the state information is obtained.

27. The method of claim 25, wherein the debug mode includes a monitor mode that causes one or more operations performed by memory controller to be performed and monitored by the debug modules.

28. The method of claim 25, wherein the state information includes one or more of current register values, instructions being performed by the memory controller, and information being transmitted over one or more internal busses of the memory subsystem.

29. The method of claim 23, wherein the memory subsystem is a flash memory package and the non-volatile memory includes flash memory.

30. The method of claim 29, wherein the flash memory includes one or more NAND flash memory dies.

31. The method of claim 23, wherein the memory subsystem is limited to performing memory operations as directed by the host controller, and wherein the host controller performs input and output operations for the board-level memory device.