Debugging a memory subsystem
First Claim
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1. A memory subsystem comprising:
- non-volatile memory;
a memory controller coupled to the non-volatile memory via a first bus;
a host interface coupled to a host controller via a second bus, wherein the host interface is configured to receive commands to be executed by the memory controller from the host controller; and
a joint test action group (JTAG) interface coupled to the host controller via a third bus, wherein the JTAG interface is configured to;
provide state information associated with the memory controller to the host controller responsive to a request from the host controller;
receive input test data from the host controller via the third bus;
send the input test data to the non-volatile memory via the first bus;
retrieve output data from the non-volatile memory via the first bus; and
send the output test data to the host controller via the third bus;
wherein the memory subsystem is configured to be coupled to a board-level memory device that includes the host controller.
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Abstract
In one implementation, a memory subsystem includes non-volatile memory, a memory controller that is communicatively connected to the non-volatile memory over a first bus, a host interface through which the memory controller communicates with a host controller over a second bus, and a joint test action group (JTAG) interface that provides the host controller with access to state information associated with the memory controller. The memory subsystem can be configured to be coupled to a board-level memory device that includes the host controller.
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Citations
31 Claims
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1. A memory subsystem comprising:
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non-volatile memory; a memory controller coupled to the non-volatile memory via a first bus; a host interface coupled to a host controller via a second bus, wherein the host interface is configured to receive commands to be executed by the memory controller from the host controller; and a joint test action group (JTAG) interface coupled to the host controller via a third bus, wherein the JTAG interface is configured to; provide state information associated with the memory controller to the host controller responsive to a request from the host controller; receive input test data from the host controller via the third bus; send the input test data to the non-volatile memory via the first bus; retrieve output data from the non-volatile memory via the first bus; and send the output test data to the host controller via the third bus; wherein the memory subsystem is configured to be coupled to a board-level memory device that includes the host controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A system comprising:
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a host controller of a board-level memory device; and one or more memory subsystems of the board-level memory device that are accessible by the host controller over a plurality of buses, each of the memory subsystems including; non-volatile memory; a memory controller coupled to the non-volatile memory via a first bus of the plurality of buses; a host interface coupled to a host controller over a second bus, wherein the host interface is configured to receive commands to be executed by the memory controller from the host controller; and a Joint Test Action Group (JTAG) interface coupled to the host controller via a third bus of the plurality of buses, wherein the JTAG interface is configured to; provide state information associated with the memory subsystem to the host controller responsive to a request form the host controller; receive input test data from the host controller via the third bus; send the input test data to the non-volatile memory via the first bus; retrieve output test data from the non-volatile memory via the first bus; and send the output test data to the host controller via the third bus. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A method comprising:
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receiving, at a host interface of a memory controller of a memory subsystem, commands to be executed by the memory controller from a host controller, wherein the host interface is coupled to the host controller via a second bus, and wherein the memory controller is coupled to non-volatile memory via a first bus; receiving, at the memory controller through a Joint Test Action Group (JTAG) interface of the memory subsystem, a command from the host controller to obtain status information for the memory subsystem and input test data, wherein the JTAG interface is coupled to the host controller via a third bus; sending the input test data to non-volatile memory via the first bus; retrieving output test data from the non-volatile memory via the first bus; sending the output test data to host controller; accessing the state information during operation of the memory subsystem; and providing the status information to the host controller, wherein the memory subsystem is coupled to a board-level memory device that includes the host controller. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31)
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Specification