Apparatus and method for using a page buffer of a memory device as a temporary cache

• US 8,880,780 B2
• Filed: 08/23/2011
• Issued: 11/04/2014
• Est. Priority Date: 02/22/2007
• Status: Expired due to Fees

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Pyeon, Hong Beom, Oh, HakJune, Kim, Kin-Ki
• Primary Examiner(s): DUDEK JR, EDWARD J
• Application Number:
  US13/215,789
• Publication Number:
  US 20110314206A1
• Time in Patent Office: 1,169 Days
• Field of Search: 711/103, 711/118, 711/154, 710/52
• US Class Current: 711/103
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4247 on a daisy chain bus

Abstract

An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller'"'"'s local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations.

Claims

1. A method for use in a system comprising a serial interconnection of first to N-th memory devices connected in-series and a memory controller configured to communicate with the interconnection, N being an integer greater than one, each of the N memory devices including a memory for storing data and being associated with a device identification, each of the N memory devices being selectable based on the device identification, each of the N memory devices being configured to transfer an enable signal received at its enable input to a successive memory device of the serial interconnection, each of the N memory devices being configured to transfer a command signal received at its signal input to the successive memory device based on device selection determination and in response to the enable signal received at its enable input, each of the N memory devices being configured to receive a clock signal at its clock input and to perform operations in response to the received clock signal, the method comprising:

at the memory controller

sending a command signal to the first memory device;

the command signal including a device address identification for device selection, an operation instruction and a memory address identification;

wherein, the device address identification, the operation instruction and the memory address identification form a modular command structure, the modular command structure being a byte basis,

at an i-th memory device of the serial interconnection, i being 1≦

i≦

N

receiving the command signal sent by the memory controller or transferred from a previous memory device, the receiving the command signal being enabled by the enable signal received at the enable input of the i-th memory device,

determining whether the i-th memory device is selected based on the device address identification included in the received command signal and the associated device identification,

in a case of determination where the i-th memory device is selected,

providing a selection determination for processing, and

in response to the selection determination for processing, processing the operation instruction included in the received command signal to access the memory included in the i-th memory device in accordance with the memory address identification included in the received command signal,

in a case of determination where the i-th memory device is not selected, forwarding the received command signal including the device address identification, the operation instruction and the memory address identification formed in a modular command structure to the signal input of the successive memory device.

2. The method of claim 1, wherein the operation instruction represented by an operation code.

3. The method of claim 1, wherein the operation instruction comprises a data write instruction.

4. The method of claim 3, wherein at the memory controller,

sending the command signal including the device address identification for device selection, the data write instruction, the memory address identification, data to be written,

wherein, the device address identification, the data write instruction, the memory address identification and the data form a modular command structure.

5. The method of claim 4, wherein at the i-th memory device, the processing the operation instruction comprises:

in response to the selection determination for processing, processing the data write instruction to write the data included in the received command signal, the data being written in the memory in accordance with the memory address identification included in the received command signal.

6. The method of claim 1, wherein the operation instruction comprises a data read instruction.

7. The method of claim 6, wherein at the memory controller,

sending the command signal including the device address identification for device selection, the data read instruction and the memory address identification,

wherein, the device address identification, the data read instruction and the memory address identification form a modular command structure.

8. The method of claim 7, wherein at the i-th memory device, the processing the operation instruction comprises:

in response to the selection determination for processing, processing the data read instruction included in the received command signal, the data stored in the memory being read out from the memory in accordance with the memory address identification included in the received command signal.

9. The method of claim 1, wherein at the i-th memory device, the determining whether the i-th memory device is selected comprises:

comparing the device address identification of the command signal to the device address associated with the i-th memory device.

10. The method of claim 9, wherein the comparing comprises:

determining whether the device address identification of the command signal matches the device address associated with the i-th memory device to provide a determination result.

11. The method of claim 10, wherein the determination result is provided as the selection determination for processing, when:

the device address identification of the command signal is identical to the device address associated with the i-th memory device.

12. A method for use in a system comprising a serial interconnection of first to N-th memory devices connected in-series and a memory controller configured to communicate with the interconnection, N being an integer greater than one, each of the N memory devices including a memory for storing data and being associated with a device identification, each of the N memory devices being selectable based on the device identification, each of the N memory devices being configured to transfer an enable signal received at its enable input to a successive memory device of the serial interconnection, each of the N memory devices being configured to transfer a command signal received at its signal input to the successive memory device based on device selection determination and in response to the enable signal received at its enable input, each of the N memory devices being configured to receive a clock signal at its clock input and to perform operations in response to the received clock signal, the method comprising:

at the memory controller

sending a first command signal to the first memory device;

the first command signal including a first device address identification for device selection, a data write instruction, a memory address identification and data to be written,

wherein, the first device address identification, the data write instruction, the memory address identification and the data form a modular command structure,

at an i-th memory device of the serial interconnection, i being 1≦

i≦

N

receiving the first command signal sent by the memory controller or propagated from a previous memory device, the receiving the first command signal being enabled by the enable signal received at the enable input of the i-th memory device,

determining whether the i-th memory device is selected based on the first device address identification included in the received first command signal and the associated device identification,

in a case of determination where the i-th memory device is selected,

providing a selection determination for processing, and

in response to the selection determination for processing, processing the data write instruction included in the received first command signal, the data included in the received first command signal being written in the memory included in the i-th memory device in accordance with the memory address identification included in the received first command signal,

in a case of determination where the i-th memory device is not selected, forwarding the received first command signal including the first device address identification, the data write instruction, the memory address identification and the data formed in a modular command structure to the signal input of the successive memory device,

at the memory controller

sending a second command signal to the first memory device;

the second command signal including a second the device address identification for device selection, a data read instruction and the memory address identification,

wherein, the second device address identification, the data read instruction and the memory address identification form a modular command structure,

at a j-th memory device of the serial interconnection, j being 1≦

j≦

N

receiving the second command signal sent by the memory controller or propagated from a previous memory device, the receiving the second command signal being enabled by the enable signal received at the enable input of the j-th memory device,

determining whether the j-th memory device is selected based on the second device address identification included in the received second command signal and the associated device identification,

in a case of determination where the j-th memory device is selected,

providing a selection determination for processing, and

in response to the selection determination for processing, processing the data read instruction included in the received second command signal, the data previously written in the memory included in the j-th memory device in accordance with the memory address identification included in the received second command signal,

in a case of determination where the j-th memory device is not selected, forwarding the received second command signal including the second device address identification, the data read instruction and the memory address identification formed in a modular command structure to the signal input of the successive memory device.

13. The method of claim 12, wherein:

at the memory controller, the sending the first command signal is performed before the sending the second command signal.

14. The method of claim 13, wherein:

after the sending the first command signal to the first memory device by the memory controller, the i-th memory device performs the receiving the first command signal and the determining whether the i-th memory device is selected.

15. The method of claim 14, wherein:

at the memory controller, after sending the first command signal, the sending the second command signal is performed.

16. The method of claim 15, wherein:

after the sending the second command signal to the first memory device by the memory controller, the j-th memory device performs the receiving the second command signal and the determining whether the j-th memory device is selected.

17. A method for use in a system comprising a serial interconnection of first to N-th memory devices connected in-series and a memory controller configured to communicate with the interconnection, the memory controller including a storage element for storing data, N being an integer greater than one, each of the N memory devices including a temporary store element for temporarily storing data and being associated with a device identification, each of the N memory devices being selectable based on the device identification, each of the N memory devices being configured to transfer an enable signal received at its enable input to a successive memory device of the serial interconnection, each of the N memory devices being configure to transfer a command received at its signal input to the successive memory device based on device selection determination and in response to the enable signal received at its enable input, each of the N memory devices being configured to receive a clock signal at its clock input and to perform operations in response to the received clock signal, the method comprising:

at the memory controller

sending a first command signal to the first memory device;

the first command signal including a first device address identification for device selection, an operation instruction for data storing and first data read from the storage element included in the memory controller,

wherein, the first device address identification, the operation instruction and the first data form a modular command structure,

at an i-th memory device of the serial interconnection, i being 1≦

i≦

N

receiving the first command signal sent by the memory controller or propagated from a previous memory device, the receiving the first command signal being enabled by the enable signal received at the enable input of the i-th memory device,

determining whether the i-th memory device is selected based on the first device address identification included in the received first command signal and the associated device identification,

in a case of determination where the i-th memory device is selected,

providing a selection determination for data storing, and

in response to the selection determination for data storing, storing the first data included in the received first command signal in the temporary store element included in the selected i-th memory device;

in a case of determination where the i-th memory device is not selected, forwarding the received first command signal including the first device address identification, the operation instruction and the first data formed in a modular command structure to the signal input of the successive memory device.

18. The method of claim 17, wherein after sending the first command signal,

at the memory controller

sending a second command signal to the first memory device;

the second command signal including a second device address identification for device selection, the an operation instruction for data storing and second data read from the storage element included in the memory controller,

wherein, the second device address identification, the operation instruction and the second data form a modular command structure,

at an j-th memory device of the serial interconnection, j being 145N

receiving the second command signal sent by the memory controller or propagated from a previous memory device, the receiving the second command signal being enabled by the enable signal received at the enable input of the j-th memory device,

determining whether the j-th memory device is selected based on the second device address identification included in the received second command signal and the associated device identification,

in a case of determination where the j-th memory device is selected,

providing a selection determination for data storing, and

in response to the selection determination for data storing, storing the second data included in the received second command signal in the temporary store element included in the selected j-th memory device;

in a case of determination where the j-th memory device is not selected, forwarding the received second command signal including the second device address identification, the operation instruction and the second data formed in a modular command structure to the signal input of the successive memory device.

19. The method of claim 18, wherein after sending the second command signal,

at the memory controller

reading back the first and second data stored in the temporary store elements included in the i-th and j-th memory devices.

20. The method of claim 19, wherein after sending the second command signal,

at the memory controller

freeing up space in the storage element storing the first and second data.

21. The method of claim 20, wherein after the freeing up space in the storage element,

at the memory controller

reading back the first and second data stored in the temporary store elements included in the i-th and j-th memory devices, the read backed first and second data being re-stored in the storage element of the memory controller.