Isolation switching for backup of registered memory

• US 8,880,791 B2
• Filed: 02/05/2014
• Issued: 11/04/2014
• Est. Priority Date: 06/01/2007
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Chen, Chi-She, Solomon, Jeffrey C., Milton, Scott H., Bhakta, Jayesh
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US14/173,242
• Publication Number:
  US 20140156920A1
• Time in Patent Office: 272 Days
• Field of Search: 711/100, 711/104, 711/111, 711/154, 711/160, 711/161, 711/162, 711/170, 711/171, 711/172
• US Class Current: 711/104
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

Certain embodiments described herein include a memory system having a register coupled to a host system and operable to receive address and control signals from the host system, a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the register, the volatile memory subsystem, and the controller. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the register to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the non-volatile memory subsystem using the controller, and is operable to selectively isolate the volatile memory subsystem from the register.

Claims

1. A memory module comprising:

a standard registered DIMM (RDIMM) interface configured to provide a first signals path for transmitting a first plurality of dual data rate synchronous DRAM (DDR SDRAM) signals between the memory module and a host system, the first plurality of DDR SDRAM signals including at least address/control and data signals;

a register coupled to the standard RDIMM interface via the first signals path, the register operable to receive DDR SDRAM address/control signals of the first plurality of DDR SDRAM signals;

a volatile memory subsystem having a first storage capacity;

a non-volatile memory subsystem having a second storage capacity that is at least 400percent more than the first storage capacity, wherein the memory module is configured to provide non-volatile storage via the non-volatile memory subsystem;

a circuit; and

a controller in communication with the circuit via a second signals path for transmitting a second plurality of DDR SDRAM signals between the controller and the circuit, the second plurality of DDR SDRAM signals including at least address/control and data signals, wherein the controller is coupled to the nonvolatile memory subsystem via a third signals path for transmitting at least data, address and control signals between the controller and the nonvolatile memory subsystem, and wherein the circuit is coupled

(i) to the volatile memory subsystem via a fourth signals path for transmitting a third plurality of DDR SDRAM signals between the volatile memory subsystem and the circuit, the third plurality of DDR SDRAM signals including at least address/control and data signals,

(ii) to the standard RDIMM interface via the first signals path for transmitting or receiving DDR SDRAM data signals of the first plurality of DDR SDRAM signals between the circuit and the host, and

(iii) to an output of the register to receive registered DDR SDRAM address/control signals from the register,

wherein in response to a first control signal from the controller the circuit (i) transmits the registered DDR SDRAM address/control signals to the volatile memory subsystem via the fourth signals path, and (ii) transfers data between the standard RDIMM interface and volatile memory subsystem using the first and fourth signals paths,

wherein the controller is operable to control data transfer between the volatile memory subsystem and the nonvolatile memory subsystem, and

wherein in response to a second control signal from the controller, the circuit uses the second and fourth signals paths to (i) communicate the second plurality of DDR SDRAM signals to the volatile memory subsystem, and (ii) communicate data from the volatile memory subsystem to the controller.

2. The memory module of claim 1, wherein the controller includes a logic element to generate address and control signals for the nonvolatile memory subsystem, and wherein the logic element performs address to address translation between the volatile memory subsystem and the nonvolatile memory subsystem.

3. The memory module of claim 1, wherein the controller is operable to perform signal level translation between the at least data, address and control signals for the nonvolatile memory subsystem and the second plurality of DDR SDRAM signals.

4. The memory module of claim 1, wherein, in response to a request by the host system, the controller transfers data from the volatile memory subsystem into the nonvolatile memory subsystem.

5. The memory module of claim 1, wherein the controller performs memory management for the nonvolatile memory subsystem, the memory management includes bad-block management and error management for memory elements of the nonvolatile memory subsystem.

6. The memory module of claim 5, wherein the controller performs error detection/correction on each data word transferred from the volatile memory subsystem into the nonvolatile memory subsystem.

7. The memory module of claim 1, wherein the standard RDIMM interface includes a standard DIMM interface of any one of a registered DIMM (RDIMM), a small-outline DIMM (SO-DIMM), an unbuffered DIMM (UDIMM), a mini-DIMM, a mini-RDIMM, a very low profile mini-DIMM, and a micro-DIMM.

8. The memory module of claim 1, wherein the nonvolatile memory subsystem comprises one or more flash memory elements, wherein the one or more flash memory elements include one or more of multi-level cell (MLC), NOR, ONE-NAND, and NAND flash memory elements.

9. The memory module of claim 1, wherein the controller includes a voltage monitor circuit to monitor a first voltage received from the host system via the standard RDIMM interface, the voltage monitor circuit transmits a first signal to other portions of the controller upon detecting a power threshold condition, and the controller responds to the first signal by accessing data on the volatile memory system and by executing a write cycle on the nonvolatile memory subsystem.

10. The memory module of claim 9, wherein executing a write cycle on the nonvolatile memory system includes transferring data from the volatile memory subsystem to the nonvolatile memory subsystem via the controller.

11. The memory module of claim 9, further comprising:

at least one capacitor configured to store a second voltage, wherein in response to the first signal, the second voltage is used to provide power to the memory module.

12. The memory module of claim 1, wherein the circuit includes dynamic on-die termination.

13. The memory module of claim 1, wherein the controller transfers data from the volatile memory subsystem into the nonvolatile memory subsystem in response to any one of a power interruption, a power failure, a power reduction, a hang-up of the host system, a reboot condition, detecting that a voltage received from the host system is below a certain threshold voltage, detecting that a voltage received from the host system is above a certain threshold voltage, and detecting that a voltage received from the host system is below a first threshold voltage and above a second threshold voltage.

14. The memory module of claim 1, wherein the volatile memory subsystem comprises two or more DDR SDRAM memory elements.

15. The memory module of claim 1, wherein the volatile memory subsystem comprises a plurality of volatile memory elements.

16. The memory module of claim 1, wherein the standard RDIMM interface is configured to electrically couple the memory module to the host system, the standard RDIMM interface includes an edge connector which fits into a memory socket of the host system, and the edge connector includes a plurality of edge connections for transmitting the first plurality of DDR SDRAM signals between the memory module and the host system.

17. The memory module of claim 1, wherein the standard RDIMM interface is configured to electrically couple the memory module to the host system, the standard RDIMM interface includes an edge connector which fits into a memory socket of the host system, and the edge connector includes a plurality of edge connections for transmitting the first plurality of DDR SDRAM signals between the memory module and the host system.

18. A method for operating a memory module that is couplable to host computer through a standard registered DIMM (RDIMM) interface, the memory module including a circuit, a register, a controller, a volatile memory subsystem and a nonvolatile memory subsystem having a storage capacity that is 400 percent more than that of the volatile memory subsystem, the method comprising:

using the RDIMM interface to transmit, along a first signals path, a first plurality of dual data rate synchronous DRAM (DDR SDRAM) signals between the memory module and a host system, the first plurality of DDR SDRAM signals including at least address/control and data signals;

delivering to the register, along the first signals path, DDR SDRAM address/control signals of the first plurality of DDR SDRAM signals;

transmitting, along a second signals path, a second plurality of DDR SDRAM signals between the controller and the circuit, the second plurality of DDR SDRAM signals including at least address/control and data signals;

transmitting, along a third signals path, at least data, address and control signals between the controller and the nonvolatile memory subsystem;

transmitting, along a fourth signals path, a third plurality of DDR SDRAM signals between the volatile memory subsystem and the circuit, the third plurality of DDR SDRAM signals including at least address/control and data signals;

transmitting or receiving, along the first signals path, DDR SDRAM data signals of the first plurality of DDR SDRAM signals between the circuit and the host;

receiving, at the circuit, registered DDR SDRAM address/control signals from an output of the register;

in response to a first control signal from the controller, operating the circuit to;

(i) transmit the registered DDR SDRAM address/control signals to the volatile memory subsystem via the fourth signals path, and

(ii) transfer data between the standard RDIMM interface and the volatile memory subsystem using the first and fourth signals paths; and

in response to a second control signal from the controller, operating the circuit to use the second and fourth signals paths to

(i) communicate the second plurality of DDR SDRAM signals to the volatile memory subsystem, and

(ii) communicate data from the volatile memory subsystem to the controller.

19. The method of claim 18, further comprising using a logic element of the controller to generate address and control signals for the nonvolatile memory subsystem and to perform address-to-address translation between the volatile memory subsystem and the nonvolatile memory subsystem.

20. The method of claim 18, further comprising operating the controller to perform signal level translation between the at least data, address and control signals for the nonvolatile memory subsystem and the second plurality of DDR SDRAM signals.

21. The method of claim 18, wherein, in response to a request by the host system, the controller transfers data from the volatile memory subsystem into the nonvolatile memory subsystem.

22. The method of claim 18, wherein the controller performs memory management for the nonvolatile memory subsystem, the memory management including bad-block management and error management for memory elements of the nonvolatile memory subsystem.

23. The method of claim 22, wherein the controller performs error detection/correction on each data word transferred from the volatile memory subsystem into the nonvolatile memory subsystem.

24. The method of claim 18, wherein the standard RDIMM interface includes a standard DIMM interface of any one of a registered DIMM (RDIMM), a small-outline DIMM (SO-DIMM), an unbuffered DIMM (UDIMM), a mini-DIMM, a mini-RDIMM, a very low profile mini-DIMM, and a micro-DIMM.

25. The method of claim 18, wherein the nonvolatile memory subsystem comprises one or more flash memory elements, and wherein the one or more flash memory elements include one or more of multi-level cell (MLC), NOR, ONE-NAND, and NAND flash memory elements.

26. The method of claim 18, wherein the controller includes a voltage monitor circuit to monitor a first voltage received from the host system via the standard RDIMM interface, the voltage monitor circuit operable to transmit a first signal to other portions of the controller upon detecting a power threshold condition, and the controller responds to the first signal by accessing data on the volatile memory system and by executing a write cycle on the nonvolatile memory subsystem.

27. The method of claim 26, wherein executing a write cycle on the nonvolatile memory system includes transferring data from the volatile memory subsystem to the nonvolatile memory subsystem via the controller.

28. The method of claim 26, further comprising:

using at least one capacitor configured to store a second voltage, wherein in response to the first signal, the second voltage is used to provide power to the memory module.

29. The method of claim 18, wherein the circuit includes dynamic on-die termination.

30. The method of claim 18, wherein the controller transfers data from the volatile memory subsystem into the nonvolatile memory subsystem in response to any one of a power interruption, a power failure, a power reduction, a hang-up of the host system, a reboot condition, detecting that a voltage received from the host system is below a certain threshold voltage, detecting that a voltage received from the host system is above a certain threshold voltage, and detecting that a voltage received from the host system is below a first threshold voltage and above a second threshold voltage.

31. The method of claim 18, wherein the volatile memory subsystem comprises two or more DDR SDRAM memory elements.

32. The method of claim 18, wherein the volatile memory subsystem comprises a plurality of volatile memory elements.