Computer system having cache subsystem performing demote requests

• US 8,880,805 B2
• Filed: 05/11/2011
• Issued: 11/04/2014
• Est. Priority Date: 12/12/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shum, Chung-Lung Kevin, Jackson, Kathryn Marie, Webb, Charles Franklin
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US13/105,235
• Publication Number:
  US 20120124292A1
• Time in Patent Office: 1,273 Days
• Field of Search: 711/125, 711/E12.002, 711/121, 711/141, 711/146, 711/145, 711/144
• US Class Current: 711/121
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0837 with software control, e.g. non-cacheable data
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/6042 Allocation of cache space to multiple users or processors
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Computer system having cache subsystem wherein demote requests are performed by the cache subsystem. Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor'"'"'s explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.

Claims

1. A computer system comprising one or more microprocessor cores each having an instruction dispatch unit, a fixed point unit and a load store unit, and a cache subsystem, the computer system configured to perform a method comprising:

executing, by a selected microprocessor core of the computer system, a demote instruction, the demote instruction specifying a cache line of the cache subsystem, wherein the selected microprocessor core has exclusive ownership of the specified cache line; and

based on the executing the demote instruction, relinquishing exclusive ownership of the cache line owned by said selected microprocessor core, the cache line specified by the demote instruction, the relinquishing causing the cache line of the cache subsystem to be any one of exclusive-to-no-one, shared or read-only.

2. The computer system according to claim 1 wherein when a demote instruction is dispatched from said instruction dispatch unit a logical address calculated according to an instruction format and a decode of such instruction indicating a demote operation is sent from the instruction decode unit to the load store unit, and the instruction dispatch unit sends the demote instruction opcode to said fixed point unit which will complete the demote instruction if the demote instruction is the next to complete without waiting for any acknowledgement or doing any architectural update.

3. The computer system according to claim 2 wherein said load store unit obtains an absolute address used in cache management by either looking up the address translation of the logical address sent from the instruction dispatch unit in its translation lookaside buffer or obtains a translation result through a dynamic translation process, and once the absolute address is obtained, the load store unit will arm the absolute address and a demote command in a fetch address register, and the demote command will be a predefined interface value on the request bus to a computer system storage controller indicating a “

demote”

is to be performed.

4. The computer system according to claim 3 wherein the control logic of said load store unit holds a demote request, and waits until all prior instructions complete before it sends the demote request and address to the storage controller by monitoring a pipeline flushing interface from the fixed point unit which controls instruction completion and such that the demote request is not sent under an incorrectly predicted branch path, or, in case, if any older instruction does not successfully complete due to processor pipeline flushing conditions, to avoid an unnecessary performance penalty may be incurred.

5. The computer system according to claim 1 wherein in an out of order selected microprocessor, due to the nature of the design, the launch of a demote request from the load store unit makes use of a tag, and a demote request in a fetch address register is tagged with an instruction ID, and only launched when the global completion logic determines that this instruction ID is being completed.

6. The computer system according to claim 1 wherein in an out of order selected microprocessor, due to the nature of the design, the launch of a demote request from the load store unit makes use of a tag, and a demote request is written into an instruction ID tagged store queue which will send out the demote request in order determined by the global completion logic without being premature.

7. The computer system according to claim 1, wherein based on the demote instruction being dispatched from said instruction dispatch unit to said fixed point unit, completing by the fixed point unit the execution of the demote instruction, the completing based on the demote instruction being the next to complete, the execution of the demote instruction being completed by the fixed point unit absent waiting for any demote instruction load store unit acknowledgement and absent waiting for any demote instruction architectural update.

8. the system according to claim 1, further comprising:

based on the executing the demote instruction, the cache subsystem requesting the exclusive ownership of the cache line from all microprocessor cores of the one or more microprocessor cores; and

based on the cache subsystem requesting the exclusive ownership and the demoting selected microprocessor core having no pending storage updates to the cache line, the cache subsystem causing cache coherency logic to demote the cache line from exclusive ownership.

9. The system according to claim 1, further comprising:

based on the demote instruction being dispatched from said instruction dispatch unit to said fixed point unit, completing by the fixed point unit the execution of the demote instruction, the completing based on the demote instruction being the next to complete, the execution of the demote instruction being completed by the fixed point unit absent waiting for any demote instruction load store unit acknowledgement and absent waiting for any demote instruction architectural update.

10. The computer system according to claim 1, further comprising:

delaying the relinquishing until there are no pending stores for the cache line in the selected microprocessor core.

11. A method in a computer system comprising one or more microprocessor cores each having an instruction dispatch unit, a fixed point unit, a load store unit and a cache subsystem, the method comprising:

executing, by a selected microprocessor core of the computer system, a demote instruction, the demote instruction specifying a cache line of the cache subsystem, wherein the selected microprocessor core has exclusive ownership of the specified cache line; and

based on the executing the demote instruction, relinquishing exclusive ownership of the cache line owned by said selected microprocessor core, the cache line specified by the demote instruction, the relinquishing causing the cache line of the cache subsystem to be any one of exclusive-to-no-one, shared or read-only.

12. The method according to claim 11 wherein when a demote instruction is dispatched from said instruction dispatch unit a logical address calculated according to an instruction format and a decode of such instruction indicating a demote operation is sent from the instruction decode unit to the load store unit, and the instruction dispatch unit sends the demote instruction opcode to said fixed point unit which will complete the demote instruction if the demote instruction is the next to complete without waiting for any acknowledgement or doing any architectural update.

13. The method according to claim 12 wherein said load store unit obtains an absolute address used in cache management by either looking up the address translation of the logical address sent from the instruction dispatch unit in its translation lookaside buffer or obtains a translation result through a dynamic translation process, and once the absolute address is obtained, the load store unit will arm the absolute address and a demote command in a fetch address register, and the demote command will be a predefined interface value on the request bus to a computer system storage controller indicating a “

demote”

is to be performed.

14. The method according to claim 13 wherein the control logic of said load store unit holds a demote request, and waits until all prior instructions complete before it sends the demote request and address to the storage controller by monitoring a pipeline flushing interface from the fixed point unit which controls instruction completion and such that the demote request is not sent under an incorrectly predicted branch path, or, in case, if any older instruction does not successfully complete due to processor pipeline flushing conditions, to avoid an unnecessary performance penalty may be incurred.

15. The method according to claim 11 wherein in an out of order selected microprocessor, due to the nature of the design, the launch of a demote request from the load store unit makes use of a tag, and a demote request in a fetch address register is tagged with an instruction ID, and only launched when the global completion logic determines that this instruction ID is being completed.

16. The method according to claim 11 wherein in an out of order selected microprocessor, due to the nature of the design, the launch of a demote request from the load store unit makes use of a tag, and a demote request is written into an instruction ID tagged store queue which will send out the demote request in order determined by the global completion logic without being premature.

17. the method according to claim 11, further comprising:

based on the executing the demote instruction, the cache subsystem requesting the exclusive ownership of the cache line from all microprocessor cores of the one or more microprocessor cores; and

based on the cache subsystem requesting the exclusive ownership and the demoting selected microprocessor core having no pending storage updates to the cache line, the cache subsystem causing cache coherency logic to demote the cache line from exclusive ownership.

18. The method according to claim 11, further comprising:

based on the demote instruction being dispatched from said instruction dispatch unit to said fixed point unit, completing by the fixed point unit the execution of the demote instruction, the completing based on the demote instruction being the next to complete, the execution of the demote instruction being completed by the fixed point unit absent waiting for any demote instruction load store unit acknowledgement and absent waiting for any demote instruction architectural update.

19. The method according to claim 11, further comprising:

delaying the relinquishing until there are no pending stores for the cache line in the selected microprocessor core.