System and method for read synchronization of memory modules

• US 8,880,833 B2
• Filed: 03/04/2013
• Issued: 11/04/2014
• Est. Priority Date: 12/29/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M., LaBerge, Paul A.
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US13/784,526
• Publication Number:
  US 20130179658A1
• Time in Patent Office: 610 Days
• Field of Search: 711/100, 711/154, 711/167
• US Class Current: 711/167
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234

Abstract

A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.

Claims

1. An apparatus, comprising:

a storage circuit configured to receive read data based, at least in part, on a first clock signal, and to provide the read data based, at least in part, on a second clock signal; and

a comparison component coupled to the storage circuit and configured to compare a first time in which the read data is received by the storage circuit with a second time in which the read data is provided from the storage circuit, the comparison component further configured to provide an adjust signal based, at least in part, on the comparison, the adjust signal indicative of a timing at which subsequent read data are provided to the storage circuit.

2. The apparatus of claim 1, further comprising:

a memory sequencer configured to receive the adjust signal and adjust the rate of the timing at which subsequent read data provided to the storage circuit based, at least in part, on the adjust signal.

3. The apparatus of claim 1, wherein the comparison component comprises:

a first counter configured to increment responsive, at least in part, to the storage circuit receiving the read data;

a second counter operable to increment responsive, at least in part, to the storage circuit providing the read data; and

a comparator configured to compare a count of the first counter and a count of the second counter to generate the adjust signal.

4. The apparatus of claim 1, wherein the storage circuit comprises a first-in first-out (FIFO) buffer.

5. The apparatus of claim 1, wherein the comparison component further configured to provide an adjust signal based, at least in part, on the comparison comprises:

the comparison component further configured to compare a read pointer and a write pointer.

6. The apparatus of claim 1, wherein the adjust signal is indicative of a crossing margin between a first time domain and a second time domain.

7. An apparatus, comprising:

a storage circuit configured receive a read data signal in accordance with a first signal and further configured to provide the read data signal in accordance with a second signal;

a write pointer configured to increment responsive, at least in part, to the first signal;

a read pointer configured to increment responsive, at least in part, to the second signal; and

a comparator configured to compare the write pointer and the read pointer to generate an adjust signal based, at least in part, on the comparison.

8. The apparatus of claim 7, wherein the first signal comprises a read clock signal and the second signal comprises a core clock signal.

9. The apparatus of claim 7, further comprising:

a signal generator coupled to the comparator and configured to receive the adjust signal, the signal generator further configured to generate one or more control signals to adjust the time at which read data is provided to the storage circuit based, at least in part, on the adjust signal.

10. The apparatus of claim 9, wherein the signal generator further configured to generate one or more control signals to adjust the time at which read data is provided to the storage circuit based, at least in part, on the adjust signal comprises:

the signal generator further configured to generate one or more control signals to adjust the time between a request being received at a first interface and the request being provided to a second interface.

11. The apparatus of claim 9, wherein the signal generator further configured to generate one or more control signals to adjust the time at which read data is provided to the storage circuit based, at least in part, on the adjust signal comprises:

the signal generator further configured to reduce the rate at which read data is provided to the storage circuit responsive to the read data being provided to the storage circuit too early and further configured to increase the rate at which read data are provided to the storage circuit responsive to the read data being provided to the storage circuit too late.

12. The apparatus of claim of claim 9, wherein the signal generator comprises a direct memory access (DMA) engine.

13. The apparatus of claim 7, wherein the storage circuit comprises a circular buffer.

14. A method, comprising:

providing data to a buffer based, at least in part, on a first signal;

providing the data from the buffer based, at least in part, on a second signal;

comparing a time at which the data is provided to the buffer and a time at which the data is provided by the buffer; and

adjusting a rate at which data is provided to the buffer based, at least in part, on the comparison.

15. The method of claim 14, further comprising:

incrementing a write pointer responsive to providing data to the buffer; and

incrementing a read pointer responsive to providing data from the buffer.

16. The method of claim 14, wherein the data is a first data, the method further comprising:

adjusting a rate at which a second data is provided to the buffer based, at least in part, on the comparison.

17. The method of claim 16, wherein adjusting a rate comprises:

reducing the rate at which the second data is provided to the buffer responsive, at least in part, to the read pointer being too proximate to the write pointer; and

increasing the rate at which the second data is provided the buffer responsive, at least in part, to the read pointer being too remote from the write pointer.

18. The method of claim 14, wherein providing the data from the buffer based, at least in part, on a second signal comprises:

providing the data from the buffer based, at least in part, on a second signal, the second signal based, at least in part, on the first signal.

19. The method of claim 14, further comprising:

providing a second data from a memory at a rate adjusted to match a timing of the second signal.

20. The method of claim 14, wherein the first signal comprises a read clock signal and the second signal comprises a core clock signal.