Computer and power management system for computer

• US 8,880,922 B2
• Filed: 03/05/2009
• Issued: 11/04/2014
• Est. Priority Date: 03/05/2009
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Siba, Yuuitirou, Ito, Hidenori
• Primary Examiner(s): Brown, Michael J
• Application Number:
  US13/147,518
• Publication Number:
  US 20120017104A1
• Time in Patent Office: 2,070 Days
• Field of Search: 713/300, 713/320, 713/323, 340/511, 340/527, 714/47.1, 714/47.2
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3246 by software initiated power-off
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

The power consumption of a computer is dynamically managed independent of the OS or applications and without any delay time caused by system control. A blade server has server blades each including a processor, a power-saving control unit and a power sensor unit; a power supply box that supplies power to the server blades; and a single service processor which defines an electric current consumption upper limit value in the power sensor unit via the power-saving control unit of each server blade. When the electric current consumption of the server blades exceeds the electric current consumption upper limit value, a signal outputted by the power sensor unit is communicated to the processor, the operating frequency of the processor is controlled, and the maximum average power is controlled to be at or below the power consumption upper limit value.

Claims

1. A computer comprising:

a processor having a normal mode that operates at a first frequency and a power-saving mode that operates at a second frequency that is lower than the first frequency;

a power-saving control unit;

a power sensor unit that measures power consumption; and

a path for supplying an interrupt signal from the power sensor unit to the power-saving control unit, wherein

the power sensor unit compares a power consumption upper limit value defined by the power-saving control unit with measured power consumption, and outputs the interrupt signal directly to the processor and to the power-saving control unit if the measured power consumption exceeds the power consumption upper limit value,

when the interrupt signal is inputted, the power saving control unit outputs to the processor a signal that is equivalent to the interrupt signal and outputs to the power sensor unit an instruction to the power sensor unit to deactivate the interrupt signal;

when the interrupt signal or the signal that is equivalent to the interrupt signal is inputted, the processor switches from the normal mode to the power-saving mode, the power sensor unit;

once the outputting of the interrupt signal is deactivated by the instruction to deactivate the interrupt signal, compares the power consumption upper limit value with a power consumption measured after outputting the interrupt signal;

if the power consumption measured after outputting the interrupt signal exceeds the power consumption upper limit value, re-outputs the interrupt signal to the processor and to the power-saving control unit;

if the power consumption measured after outputting the interrupt signal is at or below the power consumption upper limit value, does not re-output the interrupt signal to the processor and to the power-saving control unit; and

the power-saving control unit, if the interrupt signal is not re-inputted from the power sensor unit after the instruction to deactivate the interrupt signal, deactivates the signal that is equivalent to the interrupt signal.

2. A computer according to claim 1, wherein the interrupt signal comprises a processor hot signal.

3. A computer according to claim 1, wherein the computer comprises a server blade mounted on a blade server.

4. A computer according to claim 1, wherein the power sensor unit comprises a power-measuring resistor.

5. A computer according to claim 1, wherein, in the event that the power consumption of the computer exceeds the power consumption upper limit value even after the processor has switched to the power-saving mode due to the interrupt signal to the processor,

the interrupt signal is re-inputted from the power sensor unit to the power-saving control unit after the instruction to deactivate the interrupt signal, and the power-saving control unit reduces the frequency of the processor via a platform environmental control interface of the processor.

6. A computer system comprising, within one chassis, a power source, a plurality of computers according to claim 1, and a cooling fan.

7. A computer system according to claim 6, further comprising a service processor that controls the cooling fan, wherein

the power consumption upper limit value for each of the computers is defined from the service processor with respect to the power sensor unit via the power-saving control unit of each of the computers.

8. A computer system according to claim 6, wherein the interrupt signal comprises a processor hot signal.

9. A computer system according to claim 6, wherein, in the event that the power consumption of the computers exceeds the power consumption upper limit value even after the processor has been placed in the power-saving mode with the interrupt signal to the processor,

the interrupt signal is re-inputted from the power sensor unit to the power-saving control unit after the instruction to deactivate the interrupt signal, and the power-saving control unit reduces the frequency of the processor via a platform environmental control interface of the processor.

10. A power management method for a computer having a processor having a normal mode that operates at a first frequency and a power-saving mode that operates at a second frequency that is lower than the first frequency, a power-saving control unit, a power sensor unit that measures power consumption, and a path for supplying an interrupt signal from the power sensor unit to the power-saving control unit, the power management method comprising:

a step of defining a power consumption upper limit value for the computer;

a step of comparing power consumption measured by the power sensor unit with the power consumption upper limit value, and of outputting an interrupt signal from the power sensor unit directly to the processor and to the power-saving control unit when the measured power consumption exceeds the power consumption upper limit value;

a step of receiving by the power-saving control unit the interrupt signal and outputting to the processor a signal that is equivalent to the interrupt signal;

a step of outputting by the power-saving control unit to the power sensor unit an instruction to the power sensor unit to deactivate the interrupt signal, after outputting the signal that is equivalent to the interrupt signal;

a step of switching by the processor from the normal mode to the power-saving mode upon reception of the interrupt signal or of the signal that is equivalent to the interrupt signal;

a step of receiving by the power sensor unit the instruction to deactivate the interrupt signal, and once the outputting of the interrupt signal is deactivated, comparing the power consumption upper limit value with a power consumption measured after outputting the interrupt signal;

a step of re-outputting by the power sensor unit, if the power consumption measured after outputting the interrupt signal exceeds the power consumption upper limit value, the interrupt signal to the processor and the power-saving control unit;

a step of not outputting by the power sensor unit, if the power consumption measured after outputting the interrupt signal is at or below the power consumption upper limit value, the interrupt signal to the processor and the power-saving control unit; and

a step of deactivating by the power-saving control unit, if the interrupt signal is no re-inputted from the power sensor unit after the instruction to deactivate the interrupt signal, the signal that is equivalent to the interrupt signal.

11. A power management method for a computer according to claim 10, wherein, in the event that the power consumption exceeds the power consumption upper limit value even after the processor has switched to the power-saving mode due to the interrupt signal,

the interrupt signal is re-inputted from the power sensor unit to the power-saving unit after the instruction to deactivate the interrupt signal, and the power-saving control unit reduces the frequency of the processor via a platform environmental control interface of the processor.

12. A power management method for a computer according to claim 10, further comprising:

a step of outputting to the processor from the power-saving control unit, after the interrupt signal has been outputted, a signal that is equivalent to the interrupt signal; and

a step of outputting by the power-saving control unit to the power sensor unit a signal that deactivates the interrupt signal.

13. A power management method for a computer according to claim 10, wherein the computer is one of a plurality of server blades mounted on a blade server, and the power consumption upper limit value is defined from a service processor.