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Cell-level electrostatic discharge protection for an integrated circuit

  • US 8,881,085 B1
  • Filed: 06/03/2010
  • Issued: 11/04/2014
  • Est. Priority Date: 06/03/2010
  • Status: Active Grant
First Claim
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1. A method of evaluating a layout cell for electrostatic discharge (ESD) protection, the method comprising:

  • identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC);

    comparing, via a processor, the at least one feature of the layout cell to an ESD requirement for the IC; and

    indicating whether the at least one feature of the layout cell complies with the ESD requirementwherein the ESD requirement requires the layout cell to include features comprising;

    a device region comprising at least one device; and

    a substrate ring on an outer perimeter of the device region;

    wherein the substrate ring comprises at least one substrate tap, at least one via, and a portion of at least one interconnect material layer encompassing the device region and coupling a substrate material to a ground plane of the IC; and

    wherein the portion of the at least one interconnect material layer of the substrate ring is a conductive layer located above the substrate material and coupled to the at least one substrate tap within the substrate material by the at least one via.

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