Cell-level electrostatic discharge protection for an integrated circuit
First Claim
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1. A method of evaluating a layout cell for electrostatic discharge (ESD) protection, the method comprising:
- identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC);
comparing, via a processor, the at least one feature of the layout cell to an ESD requirement for the IC; and
indicating whether the at least one feature of the layout cell complies with the ESD requirementwherein the ESD requirement requires the layout cell to include features comprising;
a device region comprising at least one device; and
a substrate ring on an outer perimeter of the device region;
wherein the substrate ring comprises at least one substrate tap, at least one via, and a portion of at least one interconnect material layer encompassing the device region and coupling a substrate material to a ground plane of the IC; and
wherein the portion of the at least one interconnect material layer of the substrate ring is a conductive layer located above the substrate material and coupled to the at least one substrate tap within the substrate material by the at least one via.
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Abstract
A method of evaluating a layout cell for electrostatic discharge (ESD) protection can include identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC) and comparing the at least one feature of the layout cell to an ESD requirement for the IC. The method can include indicating whether the feature of the layout cell complies with the ESD requirement.
32 Citations
19 Claims
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1. A method of evaluating a layout cell for electrostatic discharge (ESD) protection, the method comprising:
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identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC); comparing, via a processor, the at least one feature of the layout cell to an ESD requirement for the IC; and indicating whether the at least one feature of the layout cell complies with the ESD requirement wherein the ESD requirement requires the layout cell to include features comprising; a device region comprising at least one device; and a substrate ring on an outer perimeter of the device region; wherein the substrate ring comprises at least one substrate tap, at least one via, and a portion of at least one interconnect material layer encompassing the device region and coupling a substrate material to a ground plane of the IC; and wherein the portion of the at least one interconnect material layer of the substrate ring is a conductive layer located above the substrate material and coupled to the at least one substrate tap within the substrate material by the at least one via. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A device comprising:
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a non-transitory data storage medium usable by a system comprising a processor and a memory, wherein the data storage medium stores program code that, when executed by the system, causes the system to execute operations for evaluating a layout cell for electrostatic discharge (ESD) protection, the operations comprising; identifying at least one feature of a layout cell for use in implementing an integrated circuit (IC); comparing the at least one feature of the layout cell to an ESD requirement for the IC; and indicating whether the at least one feature of the layout cell complies with the ESD requirement; wherein the ESD requirement requires the layout cell to include features comprising; a device region comprising at least one device; and a substrate ring on an outer perimeter of the device region; wherein the substrate ring comprises at least one substrate tap, at least one via, and a portion of at least one interconnect material layer encompassing the device region and coupling a substrate material to a ground plane of the IC; and wherein the portion of the at least one interconnect material layer of the substrate ring is a conductive layer located above the substrate material and coupled to the at least one substrate tap within the substrate material by the at least one via. - View Dependent Claims (9, 10, 11, 12, 13)
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14. An integrated circuit (IC), comprising:
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a device region comprising at least one device; and a substrate ring on an outer perimeter of the device region; wherein the substrate ring comprises at least one substrate tap, at least one via, and a portion of at least one interconnect material layer encompassing the device region and coupling a substrate material to a ground plane of the IC; and wherein the portion of the at least one interconnect material layer of the substrate ring is a conductive layer located above the substrate material and coupled to the at least one substrate tap within the substrate material by the at least one via. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification