Redeposition control in MRAM fabrication process

• US 8,883,520 B2
• Filed: 06/22/2012
• Issued: 11/11/2014
• Est. Priority Date: 06/22/2012
• Status: Active Grant

• Current Assignee: Avalanche Technology Incorporated
• Original Assignee: Avalanche Technology Incorporated
• Inventors: Satoh, Kimihiro, Jung, Dong Ha, Abedifard, Ebrahim, Keshtbod, Parviz, Huai, Yiming, Zhang, Jing
• Primary Examiner(s): Vu, David
• Application Number:
  US13/530,381
• Publication Number:
  US 20130341801A1
• Time in Patent Office: 872 Days
• Field of Search: 438/3, 257/295, 257/421, 257/E21.665, 257/E21.585, 365/158
• US Class Current: 438/3
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

Claims

1. A method of fabricating memory cells comprising:

patterning a set of landing pads for the memory cells on a wafer;

depositing a dielectric film over the wafer;

etching selected holes through the dielectric film using a mask having gaps positioned over the dielectric film above a selected central area of an upper surface of each landing pad, the etching leaving the selected central area of the upper surface of each landing pad exposed;

depositing metal over the wafer and into the holes in the dielectric film to form metal studs in electrical contact with the upper surface of each landing pad; and

patterning a multi-layered memory cell pillar including a bottom electrode over each metal stud so that the metal stub provides electrical connection between the bottom electrode and the landing pad under the metal stud.

2. The method of claim 1 wherein the gaps positioned over the dielectric film above a selected central area of an upper surface of each landing pad are smaller in horizontal area than the upper surface of the landing pad.

3. The method of claim 1 further comprising actions performed after depositing metal over the wafer and into the holes in the dielectric film and before patterning a multi-layered memory cell pillar, including:

performing a first CMP process to planarize the wafer surface, the first CMP process leaving at least some metal studs having an upper surface recessed from an upper surface of dielectric material around the metal studs;

depositing a touch-up metal layer over the wafer; and

performing a second CMP process to remove the touch-up metal layer from the dielectric material around the metal studs while leaving residual touch-up metal on at least some of the metal studs metal studs to improve planarization.

4. The method of claim 1 wherein the memory cell pillars are oval-shaped in a top plan view and have a long axis orientation parallel to a direction of a bit line, the method further comprising forming an oval-shaped via above each memory cell pillar after patterning the memory cell pillars, filling the oval-shaped via with metal, then fabricating an interconnection to connect metal in the oval-shaped via to a bit line.