Self-powered integrated circuit with multi-junction photovoltaic cell

• US 8,883,541 B2
• Filed: 07/08/2013
• Issued: 11/11/2014
• Est. Priority Date: 08/25/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chen, Yuanning, Conroy, Thomas P., DeBord, Jeffrey R., Sridhar, Nagarajan
• Primary Examiner(s): Abdelaziez, Yasser A
• Application Number:
  US13/936,640
• Publication Number:
  US 20130295711A1
• Time in Patent Office: 491 Days
• Field of Search: None
• US Class Current: 438/59
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 31/0288 characterised by the doping material
• CPC Class Codes: H01L 31/0687 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/1812 including only AIVBIV alloys, e.g. SiGe
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion.

Claims

1. A method of forming an integrated circuit and photovoltaic cell, comprising:

doping an upper region of a front side of a first wafer of given conductivity type with dopant of both the given and opposite conductivity types to form well regions and source/drain regions of PMOS and NMOS transistors;

forming first and second contacts for the PMOS and NMOS transistors;

forming one or more dielectric layers over the well regions, source/drain regions and first and second contacts;

forming first and second interconnects to establish respective electrical connections between the first and second contacts and an upper part of the one or more dielectric layers;

bonding the first wafer at the upper part of the one or more dielectric layers to a second wafer;

forming a region silicon germanium material at a first depth, a region of silicon carbon material at a second depth, and a region of silicon material substantially free of germanium or carbon atoms between the first and second depths over a back side of the first wafer; and

forming regions of opposite conductivity type defining first doped regions of respective pn junctions in series of a photovoltaic cell in each of the regions of silicon germanium, silicon and silicon carbon material, with a second doped region of each of the pn junctions in series being at least partially defined by a second doped region of the given conductivity type of the wafer; and

forming first and second contacts for establishing respective electrical connections between uppermost and lowermost ones of the regions of given and opposite conductivity types of the pn junctions and the first and second interconnects.

2. The method of claim 1, wherein forming at least one of the first and second contacts for establishing electrical connections between the pn junction regions and the first and second interconnects includes forming a via contact from a location at a bottom part of the upper region to the upper part of the one or more dielectric layers.

3. The method of claim 2, wherein the via contact is formed prior to the bonding.

4. The method of claim 1, wherein forming at least one of the first and second contacts for establishing electrical connections between the pn junction regions and the first and second interconnects includes forming a wraparound contact that wraps around sides of the first wafer.